RECONFIGURABLE ON-CHIP MEMORY BANK, RECONFIGURABLE ON-CHIP MEMORY, SYSTEM-ON-CHIP HAVING SAME MOUNTED THEREON, AND METHOD FOR USING RECONFIGURABLE ON-CHIP MEMORY
A reconfigurable on-chip memory bank, reconfigurable on-chip memory, system-on-chip having same mounted thereon, and method for using reconfigurable on-chip memory is provided. The reconfigurable on-chip memory bank comprises a cell array in which a plurality of cells are arranged and data are stored, a first path unit configured to move data in the cell array, a second path unit configured to move data in the cell array and a bank controller operably coupled with the first and second path units, and configured to determine, according to a path control signal during runtime, data path which data are to be transmitted to or received from, to use a first address system when the first path unit is determined to be the data path, and to use a second address system different from the first address system when the second path unit is determined to be the data path.
1 . A system-on-chip having a reconfigurable on-chip memory mounted thereon, comprising:
a plurality of processing units; and
an on-chip memory comprising a dedicated area for each of the plurality of processing units and a common area shared by at least two ( 2 ) of the plurality of processing units,
wherein a size of the dedicated area and a size of the common area change during runtime.
2 . The system-on-chip having a reconfigurable on-chip memory mounted thereon of claim 1 , wherein the on-chip memory comprises:
a plurality of scratch pads included in the dedicated area; and
a plurality of memory units included in the dedicated area or the common area.
3 . The system-on-chip having a reconfigurable on-chip memory mounted thereon of claim 1 , wherein
each of a first calculation task processed by at least one of the plurality of processing units and a second calculation task processed by at least one other processing unit of the plurality of processing units includes at least one of a deep learning training task or a deep learning inference task.
4 . The system-on-chip having a reconfigurable on-chip memory mounted thereon of claim 2 , wherein
the plurality of memory units includes at least one first memory unit included in the dedicated area and at least one second memory unit included in the common area,
the at least one first memory unit operates in a scratch pad type, and
the at least one second memory unit operates in a shared memory type.
5 . The system-on-chip having a reconfigurable on-chip memory mounted thereon of claim 4 , wherein, during runtime, at least one of the at least one first memory unit changes operation to the shared memory type and is included in the common area.
6 . The system-on-chip having a reconfigurable on-chip memory mounted thereon of claim 4 , wherein, during runtime, at least one of the at least one second memory unit changes operation to the scratch pad type and is included in the dedicated area.
7 . The system-on-chip having a reconfigurable on-chip memory mounted thereon of claim 4 , wherein a first scratch pad among the plurality of scratch pads included in the dedicated area and a memory unit among the at least one first memory unit corresponding to the first scratch pad logically operate as a single scratch pad memory.
8 . The system-on-chip having a reconfigurable on-chip memory mounted thereon of claim 4 , wherein the at least one first memory unit is shared by two (2) processing units and by two scratch pads respectively corresponding to the two (2) processing units.
9 . The system-on-chip having a reconfigurable on-chip memory mounted thereon of claim 4 , wherein a ratio between the at least one first memory unit and the at least one second memory unit is adjustable.
10 . The system-on-chip having a reconfigurable on-chip memory mounted thereon of claim 2 , wherein,
the plurality of memory units includes at least one first memory unit included in the dedicated area and at least one second memory unit included in the common area,
at least one first memory unit included in the dedicated area is controlled by a scratch pad controller that controls data exchange between a memory unit and a scratch pad, and
at least one second memory unit included in the common area is controlled by a global controller that controls data exchange between a memory unit and a data bus.
11 . A method of using a system-on-chip having a reconfigurable on-chip memory mounted thereon and comprising a plurality of processing units, the method comprising:
assigning a first calculation task to at least one first processing unit of the plurality of processing units;
assigning a second calculation task to at least one second processing unit of the plurality of processing units; and
changing, during runtime, a size of a dedicated area for each of the plurality of processing units and a size of a common area shared by at least two (2) of the plurality of processing units.
12 . The method of claim 11 , wherein the on-chip memory comprises:
a plurality of scratch pads included in the dedicated area; and
a plurality of memory units included in the dedicated area or the common area.
13 . The method of claim 11 , wherein each of the first calculation task and the second calculation task includes at least one of a deep learning training task or a deep learning inference task.
14 . The method of claim 12 , further comprising:
operating, at least one first memory unit of the plurality of memory units included in the dedicated area, in a scratch pad type; and
operating, at least one second memory unit of the plurality of memory units included in the common area, in a shared memory type.
15 . The method of claim 14 , wherein the changing the size of the dedicated area and the size of the common area during runtime comprises, changing, an operation of at least one of the at least one first memory unit, to the shared memory type during runtime.
16 . The method of claim 14 , wherein the changing the size of the dedicated area and the size of the common area during runtime comprises, changing, an operation of at least one of the at least one second memory unit, to the scratch pad type during runtime.
17 . The method of claim 14 , wherein a first scratch pad among the plurality of scratch pads included in the dedicated area and a memory unit among the at least one first memory unit corresponding to the first scratch pad logically operate as a single scratch pad memory.
18 . The method of claim 14 , wherein the at least one first memory unit is shared by two (2) processing units and by two scratch pads respectively corresponding to the two (2) processing units.
19 . The method of claim 14 , wherein the changing the size of the dedicated area and the size of the common area during runtime comprises adjusting a ratio between the at least one first memory unit and the at least one second memory unit.
20 . The method of claim 12 , wherein,
the plurality of memory units includes at least one first memory unit included in the dedicated area and at least one second memory unit included in the common area,
the at least one first memory unit included in the dedicated area is controlled by a scratch pad controller that controls data exchange between a memory unit and a scratch pad, and
the at least one second memory unit included in the common area is controlled by a global controller that controls data exchange between a memory unit and a data bus.