Reactive Dynamic Read Retry
A method and associated memory system for operating a memory controller. The method reads the data from the memory using a progression of hard reads of the data; utilizes in the progression a set of hard read retry entries including at least a first hard read retry entry and a second hard read retry entry, each of the hard reads performed with a different hard read bias based on the set of the hard read retry entries; continues the progression until a successful read occurs or for a predetermined number times of unsuccessful hard reads; records a read bias used for the successful read and checksums of all unsuccessful hard reads; and after the successful read, replaces the first hard read retry entry with the read-bias of the successful read.
1 . A method for operating a memory controller, comprising:
reading data from the memory using a progression of hard reads of the data;
utilizing in the progression a set of hard read retry entries including at least a first hard read retry entry and a second hard read retry entry, each of the hard reads performed with a different hard read bias based on the set of the hard read retry entries;
continuing the progression until a successful read occurs or for a predetermined number times of unsuccessful hard reads;
recording a read bias used for the successful read and checksums of all unsuccessful hard reads; and
after the successful read, replacing the first hard read retry entry with the read-bias of the successful read.
2 . The method of claim 1 , further comprising after the successful read, reordering the set of hard read retry entries in an ascending order according to a magnitude of the checksums.
3 . The method of claim 2 , further comprising averaging the checksums for each page of the data read to obtain an averaged checksum.
4 . The method of claim 2 , further comprising averaging for each page of the data read, for a predetermined number of past reads, the checksums to obtain a windowed averaged checksum.
5 . The method of claim 1 , further comprising:
when all the hard reads up to the predetermined number times are unsuccessful, soft reading the data using a voltage threshold optimization to obtain the successful read.
6 . The method of claim 5 , wherein the soft reading obtains a center read bias of a program-voltage distribution for each NAND page as an optimal read bias, and
the optimal read bias is used to update the set of hard read retry entries according to a shift of the program-voltage distribution of the NAND page.
7 . The method of claim 5 , wherein the optimal read bias found by the voltage threshold optimization becomes the first hard read entry, and
the hard read entry with a largest distance to the optimal read bias is removed from the set of hard read retry entries.
8 . The method of claim 5 , further comprising updating all the hard read entries in the set of hard read retry entries by replacing the first hard read entry with the optimal read bias and shifting at least the second hard read entry in a direction toward the optimal read biases.
9 . The method of claim 1 , further comprising:
when the read-bias of the successful soft read is different from all existing hard read retry entries, removing the hard read retry entry from the set of hard read retry entries that has the largest checksum.
10 . The method of claim 1 , wherein the reading of the data from the memory comprises reading the data for different blocks of the memory and identifying effective entries in the set of hard read retry entries which successfully read the different blocks.
11 . A memory system comprising:
a memory device; and
a controller in communication with and configured to control the memory device, wherein the controller is configured to:
read data from the memory using a progression of hard reads of the data;
utilize in the progression a set of hard read retry entries including at least a first hard read retry entry and a second hard read retry entry, each of the hard reads performed with a different hard read bias based on the set of the hard read retry entries;
continue the progression until a successful read occurs or for a predetermined number times of unsuccessful hard reads;
recording a read bias used for the successful read and checksums of all unsuccessful hard reads; and
after the successful read, replacing the first hard read retry entry with the read-bias of the successful read.
12 . The memory system of claim 11 , wherein the controller, after the successful read, is configured to reorder the set of hard read retry entries in an ascending order according to a magnitude of the checksums.
13 . The memory system of claim 12 , wherein the controller is configured to average the checksums for each page of the data read to obtain an averaged checksum.
14 . The memory system of claim 12 , wherein the controller is configured to average for each page of the data read, for a predetermined number of past reads, the checksums to obtain a windowed averaged checksum.
15 . The memory system of claim 11 , wherein the controller is configured to, if all the hard reads up to the predetermined number times are unsuccessful, soft read the data using a voltage threshold optimization to obtain the successful read.
16 . The memory system of claim 15 , wherein the controller is configured to:
obtain a center read bias of a program-voltage distribution for each NAND page as an optimal read bias; and
use the optimal read bias to update the set of hard read retry entries according to a shift of the program-voltage distribution of the NAND page.
17 . The memory system of claim 15 , wherein the controller is configured to use the optimal read bias as the first hard read entry, and remove from the set of hard read retry entries the hard read entry with a largest distance to the optimal read bias.
18 . The memory system of claim 15 , wherein the controller is configured to update all the hard read entries in the set of hard read retry entries by replacing the first hard read entry with the optimal read bias and shift at least the second hard read entry in a direction toward the optimal read biases.
19 . The memory system of claim 11 , wherein the controller is configured to, when the read-bias of the successful soft read is different than all existing hard read retry entries, remove the hard read retry entry from the set of hard read retry entries that has the largest checksum.
20 . The memory system of claim 11 , wherein the controller is configured to read the data for different blocks of the memory and identify effective entries in the set of hard read retry entries which successfully read the different blocks.