PIPELINE PROTECTION FOR CPUS WITH SAVE AND RESTORE OF INTERMEDIATE RESULTS
Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.
1 . A circuit device comprising:
a set of pipeline stages configurable to execute a load instruction and a second instruction;
a memory coupled to the set of pipeline stages, wherein the memory has a latency; and
a hazard circuit coupled to the set of pipeline stages and to the memory and configurable to:
receive an indication from the memory of whether data associated with the load instruction will be returned within the latency of the memory; and
determine whether to stall execution of the second instruction by the set of pipeline stages based on:
whether the second instruction would attempt to utilize the data associated with the load instruction within the latency of the memory; and
whether the second instruction would attempt to utilize the data associated with the load instruction and the indication specifies that the data will not be returned within the latency of the memory.
2 . The circuit device of claim 1 , wherein:
the set of pipeline stages is configurable to provide a request for the data in response to the load instruction; and
the request for the data includes a transaction identifier.
3 . The circuit device of claim 2 , wherein the memory is configurable to provide the transaction identifier to the set of pipeline stages with the data.
4 . The circuit device of claim 1 , wherein the set of pipeline stages is configurable to execute a third instruction while the second instruction is stalled.
5 . The circuit device of claim 4 , wherein:
the load instruction is a first load instruction;
the third instruction is a second load instruction; and
the memory is configurable to service the second load instruction as a hit-under-miss with respect to the first load instruction.
6 . The circuit device of claim 1 , wherein the hazard circuit is configurable to:
track a predetermined number of outstanding load instructions; and
determine whether to stall the execution of the second instruction further based on whether the load instruction exceeds the predetermined number of outstanding load instructions.
7 . The circuit device of claim 1 , wherein the memory is a level-one (L1) cache.
8 . The circuit device of claim 1 , wherein:
the memory is a first memory;
the circuit device further comprises a second memory coupled to the hazard circuit;
the set of pipeline stages is configurable to execute a third instruction; and
the hazard circuit is further configurable to:
detect a hazarding condition with respect to the third instruction;
based on the hazarding condition, cause the set of pipeline stages to store an intermediate result of the third instruction in the second memory; and
based on the hazarding condition being resolved, restore the intermediate result of the third instruction to the set of pipeline stages from the second memory.
9 . The circuit device of claim 8 , wherein:
the circuit device includes a set of memory devices that includes the second memory; and
each stage of the set of pipeline stages is coupled to a respective memory device of the set of memory devices.
10 . The circuit device of claim 8 , wherein the hazard circuit is configurable to:
maintain a lifetime tracking value for the third instruction; and
determine where in the set of pipeline stages to restore the intermediate result of the third instruction based on the lifetime tracking value.
11 . A device comprising:
a processor that includes:
a set of functional units configurable to execute a load instruction, a second instruction, a third instruction, and a fourth instruction;
a first memory coupled to the set of functional units, wherein the first memory has a latency;
a second memory; and
a hazard circuit coupled to the set of pipeline stages and to the second memory and configurable to:
determine whether the second instruction utilizes a set of data returned by the load instruction;
receive, from the first memory, an indication of whether the set of data will be returned within the latency of the first memory;
determine whether to stall execution of the second instruction based on whether the set of data will be returned within the latency of the first memory;
determine whether the third instruction and the fourth instruction write to a same location within the first memory; and
determine whether to store a result of the fourth instruction in the second memory until the third instruction completes based on whether the third instruction and the fourth instruction write to a same location within the first memory.
12 . The device of claim 11 , wherein the hazard circuit is configurable to stall the second instruction based on either: the second instruction would attempt to utilize the set of data of the load instruction within the latency of the first memory or the set of data will not be returned within the latency of the first memory.
13 . The device of claim 11 , wherein the hazard circuit is configurable to:
track a predetermined number of outstanding load instructions; and
stall the execution of the second instruction further when the load instruction exceeds the predetermined number of outstanding load instructions.
14 . The device of claim 11 , wherein hazard circuit is configurable to, after completion of the third instruction, cause the result of the fourth instruction to be provided by the second memory and stored in the first memory.
15 . A method comprising:
receiving, from a memory, an indication of whether a set of data will be received within a latency period of the memory; and
determining whether to stall a second instruction that utilizes the set of data based on whether the set of data will be received within the latency period.
16 . The method of claim 15 , wherein the determining of whether to stall the second instruction is further based on whether the second instruction would attempt to utilize the set of data during the latency period associated with the set of data.
17 . The method of claim 15 further comprising:
providing, to the memory, a transaction identifier associated with the set of data; and
receiving, from the memory, the transaction identifier in conjunction with the set of data.
18 . The method of claim 15 further comprising:
stalling the second instruction; and
executing a third instruction while the second instruction is stalled.
19 . The method of claim 15 , wherein the determining of whether to stall the second instruction is further based on whether a load instruction associated with the set of data exceeds a predetermined number of outstanding load instructions.
20 . The method of claim 15 , wherein the memory is a level-one (L1) cache.