METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.
1 . A device, comprising:
a cache system comprising:
a victim cache store queue including a first set of banks; and
a victim storage coupled to the victim cache store queue and including a second set of banks, wherein the second set of banks is configured to be accessed independently and in parallel.
2 . The device of claim 1 , wherein at least one of the first set of banks or the second set of banks includes 16 banks.
3 . The device of claim 1 , wherein at least one of the first set of banks or the second set of banks includes a bank configured to store 64 bits.
4 . The device of claim 1 , wherein the first set of banks is configured to be accessed independently and in parallel.
5 . The device of claim 1 , wherein each of the first set of banks is coupled to a respective one of the second set of banks.
6 . The device of claim 1 , wherein the cache system comprises a tag memory including a set of ports each associated with a respective datapath of a set of datapaths to receive a respective operation.
7 . The device of claim 6 , wherein the tag memory is configured to determine in parallel whether the respective operation of each port of the set of ports corresponds to a hit or a miss.
8 . The device of claim 7 , wherein the tag memory is configured to:
for the respective operation of a first port of the set of ports that is associated with a first datapath of the set of datapaths,
determine that the respective operation corresponds to a hit;
determine that the respective operation is further associated with an address received from a finite-state machine associated with the first datapath; and
convert the hit to a miss.
9 . The device of claim 7 , wherein the tag memory is configured to:
for the respective operation of a first port of the set of ports that is associated with a first datapath of the set of datapaths,
determine that the respective operation corresponds to a miss;
determine that the respective operation is further associated with an address received from a finite-state machine associated with the first datapath; and
convert the miss to a hit.
10 . The device of claim 6 , wherein the set of datapaths includes a first datapath associated with scalars and a second datapath associated with vectors.
11 . A system, comprising:
a processor core; and
a cache system coupled to the processor core and including:
a victim cache store queue including a first set of banks; and
a victim storage coupled to the victim cache store queue and including a second set of banks, wherein the second set of banks is configured to be accessed independently and in parallel.
12 . The system of claim 11 , wherein at least one of the first set of banks or the second set of banks includes 16 banks.
13 . The system of claim 11 , wherein at least one of the first set of banks or the second set of banks includes a bank configured to store 64 bits.
14 . The system of claim 11 , wherein the first set of banks is configured to be accessed independently and in parallel.
15 . The system of claim 11 , wherein each of the first set of banks is coupled to a respective one of the second set of banks.
16 . The system of claim 11 , wherein the cache system comprises a tag memory including a set of ports each associated with a respective datapath of a set of datapaths to receive a respective operation.
17 . The system of claim 16 , wherein the tag memory is configured to determine in parallel whether the respective operation of each port of the set of ports corresponds to a hit or a miss.
18 . The system of claim 17 , wherein the tag memory is configured to:
for the respective operation of a first port of the set of ports that is associated with a first datapath of the set of datapaths,
determine that the respective operation corresponds to a hit;
determine that the respective operation is further associated with an address received from a finite-state machine associated with the first datapath; and
convert the hit to a miss.
19 . The system of claim 17 , wherein the tag memory is configured to:
for the respective operation of a first port of the set of ports that is associated with a first datapath of the set of datapaths,
determine that the respective operation corresponds to a miss;
determine that the respective operation is further associated with an address received from a finite-state machine associated with the first datapath; and
convert the miss to a hit.
20 . The system of claim 16 , wherein the set of datapaths includes a first datapath associated with scalars and a second datapath associated with vectors.