LEVEL SHIFTING IN ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A MEMORY SUB-SYSTEM
Control logic causes, during a program operation, a programming pulse to be applied to a memory cell of a set of memory cells to be programmed to a first programming level of a set of programming levels. The control logic further determines that a condition associated with the memory cell is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.
1 . A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing, during a program operation, a programming pulse to be applied to a memory cell of a set of memory cells to be programmed to a first programming level of a set of programming levels, wherein the programming pulse programs each programming level of the set of programming levels associated with the set of memory cells;
determining that a condition associated with the memory cell is satisfied; and
executing a level shifting operation associated with the memory cell in response to the condition being satisfied.
2 . The memory device of claim 1 , wherein the condition is satisfied when a threshold voltage of the memory cell is greater than a first program verify voltage level and less than a second program verify voltage level.
3 . The memory device of claim 2 , wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is lower than the first programming level.
4 . The memory device of claim 1 , wherein the condition is satisfied when a threshold voltage of the memory cell is greater than a first program verify voltage level and a second program verify voltage level and less than a third program verify voltage level of one or more program verify voltage levels of a program verify operation.
5 . The memory device of claim 4 , wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is more than one programming level lower than the first programming level.
6 . The memory device of claim 1 , wherein the level shifting operation causes a first bitline voltage level associated with a first bitline corresponding to the memory cell to be adjusted.
7 . The memory device of claim 1 , wherein the condition is satisfied when a threshold voltage of the memory cell is less than a first program verify voltage level associated with a second programming level that is lower than the first programming level.
8 . The memory device of claim 7 , wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is higher than the first programming level.
9 . A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing, during a program operation, a programming pulse to be applied to a set of memory cells of the memory array to be programmed to a target programming distribution associated with a first programming level of a set of programming levels, wherein the programming pulse programs each programming level of the set of programming levels;
identifying a first subset of the set of memory cells in a first region of a programming distribution associated with the first programming level following application of the programming pulse; and
executing a level shifting operation associated with the first subset of the set of memory cells in the first region.
10 . The memory device of claim 9 , wherein the first subset of the set of memory cells in the first region are associated with a threshold voltage that is greater than a first program verify voltage level and less than a second program verify voltage level.
11 . The memory device of claim 10 , wherein executing the level shifting operation comprises logically shifting a designation associated with the first subset of the set of memory cells to a second programming level that is lower than the first programming level.
12 . The memory device of claim 9 , wherein the first subset of the set of memory cells in the first region are associated with a threshold voltage that is less than a program verify voltage level associated with a programming level that is lower than the first programming level.
13 . The memory device of claim 12 , wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is higher than the first programming level.
14 . A method comprising:
causing, during a program operation associated with a set of memory cells of a memory device, a first programming pulse to be applied to a memory cell of the set of memory cells to be programmed to a first programming level of a set of programming levels, wherein the first programming pulse programs each programming level of the set of programming levels associated with the set of memory cells;
determining that a condition associated with the memory cell is satisfied; and
executing a level shifting operation associated with the memory cell in response to the condition being satisfied.
15 . The method of claim 14 , wherein the condition is satisfied when a threshold voltage of the memory cell is greater than a first program verify voltage level and less than a second program verify voltage level.
16 . The method of claim 15 , wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is lower than the first programming level.
17 . The method of claim 14 , wherein the condition is satisfied when a threshold voltage of the memory cell is greater than a first program verify voltage level and a second program verify voltage level and less than a third program verify voltage level of one or more program verify voltage levels of a program verify operation.
18 . The method of claim 17 , wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is more than one programming level lower than the first programming level.
19 . The method of claim 14 , wherein the level shifting operation causes a first bitline voltage level associated with a first bitline corresponding to the memory cell to be adjusted.
20 . The method of claim 14 , wherein the condition is satisfied when a threshold voltage of the memory cell is less than a first program verify voltage level associated with a second programming level that is lower than the first programming level; and wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is higher than the first programming level.