SYSTEM AND METHOD FOR PROGRESSIVE READ AND SOFT DECODING FOR MEMORY DEVICES
A memory system includes a memory device including one or more memory cells for storing data, and a controller coupled to the memory device. The controller is configured to: perform at least first and second read operations on the data of the memory cells using first and second read voltages, respectively, in response to a read command, to generate first and second read values; determine a best read value among the first and second read values; generate at least one log-likelihood ratio (LLR) value based on the first and second read values; and perform a soft decoding based on the best read value and the LLR values
1 . A memory system comprising:
a memory device including one or more memory cells for storing data; and
a controller coupled to the memory device and configured to:
perform at least first and second read operations on the data of the memory cells using first and second read voltages, respectively, in response to a read command, to generate first and second read values;
determine a best read value among the first and second read values;
generate at least one log-likelihood ratio (LLR) value based on the first and second read values; and
perform a soft decoding based on the best read value and the LLR values.
2 . The memory system of claim 1 , wherein the controller
performs the first hard read operation,
performs a first hard decoding on the first hard read value, and
when it is determined that the first hard decoding failed, performs the second hard read operation to output the second hard read value.
3 . The memory system of claim 1 , wherein the controller determines, as the best read value, one read value with a least checksum value, among the first and second read values.
4 . The memory system of claim 1 , wherein each of the first and second read values includes multiple bits, and
the controller generates the at least one LLR value based on whether corresponding bits of the first read value and the second read value are consistent.
5 . The memory system of claim 1 , wherein each of the first and second read values includes multiple bits, and
the controller generates the at least one LLR value based on checksums on bits of the first read value and the second read value.
6 . The memory system of claim 1 , wherein the controller is further configured to determine whether the soft decoding succeeds.
7 . The memory system of claim 1 , wherein, when it is determined that the soft decoding failed, the controller is further configured to:
perform at least one additional read operation;
determine the best read value;
generate the at least one LLR value; and
perform the soft decoding.
8 . The memory system of claim 7 , wherein, when the soft decoding failed a set number of times,
the controller is further configured to search for an optimal central voltage threshold (Vt) of each valley of a program voltage (PV) distribution.
9 . The memory system of claim 8 , wherein the controller is further configured to:
when it is determined that a checksum of the best read is greater than a threshold value, perform the search for the optimal central voltage threshold.
10 . The memory system of claim 8 , wherein the controller is further configured to determine the best read value, generate the at least one LLR value, and perform the soft decoding, based on the optimal central voltage threshold.
11 . A method for operating a memory system including a memory device including one or more memory cells for storing data, and a controller coupled to the memory device, comprising:
performing at least first and second read operations on the data of the memory cells using first and second read voltages, respectively, in response to a read command, to generate first and second read values;
determining a best read value among the first and second read values;
generating at least one log-likelihood ratio (LLR) value based on the first and second read values; and
performing a soft decoding based on the best read value and the LLR values.
12 . The method of claim 11 , wherein the performing of the at least first and second read operations includes:
performing the first hard read operation,
performing a first hard decoding on the first hard read value, and
when it is determined that the first hard decoding failed, performing the second hard read operation to output the second hard read value.
13 . The method of claim 11 , wherein the determining of the best read value includes determining, as the best read value, one read value with a least checksum value, among the first and second read values.
14 . The method of claim 11 , wherein each of the first and second read values includes multiple bits, and
the at least one LLR value is generated based on whether corresponding bits of the first read value and the second read value are consistent.
15 . The method of claim 11 , wherein each of the first and second read values includes multiple bits, and
the at least one LLR value is generated based on checksums on bits of the first read value and the second read value.
16 . The method of claim 11 , further comprising determining whether the soft decoding succeeds.
17 . The method of claim 11 , further comprising:
when it is determined that the soft decoding failed,
performing at least one additional read operation;
determining the best read value;
generating the at least one LLR value; and
performing the soft decoding.
18 . The method of claim 17 , further comprising:
when the soft decoding failed a set number of times,
searching for an optimal central voltage threshold (Vt) of each valley of a program voltage (PV) distribution.
19 . The method of claim 18 , further comprising:
when it is determined that a checksum of the best read is greater than a threshold value,
performing the search for the optimal central voltage threshold.
20 . The method of claim 18 , further comprising:
determining the best read value, generating the at least one LLR value, and performing the soft decoding, based on the optimal central voltage threshold.