Interleaved memory transaction tracking for transactions with unrelated lengths
A first series of memory access transactions are received from a first set of compressed data having a number of first transactions indeterminate in a transaction receiver, and a second series of memory access transactions are received from a second set of compressed data having a number of second transactions indeterminate in the transaction receiver. A count of outstanding transactions for the combined first and second sets of compressed data is received in the transaction receiver, and memory space is allocated for the first and second series of transactions based at least in part on the received count of outstanding combined transactions. The first series of transactions are stored sequentially from a first end of the allocated memory space and the second series of transactions are stored sequentially from a second end of the allocated memory space opposite the first end.
1 . A method comprising:
receiving a first series of memory access transactions from a first set of compressed data having a number of first transactions indeterminate in a transaction receiver;
receiving a second series of memory access transactions from a second set of compressed data having a number of second transactions indeterminate in the transaction receiver;
receiving a count representing outstanding transactions for a combination of first set of compressed data and the second set of compressed data in the transaction receiver; and
allocating first memory space for the first series of transactions and the second series of transactions based at least in part on the received count representing outstanding transactions for the combination of the first set of compressed data and the second set of compressed data such that the first series of transactions are stored sequentially from a first end of the allocated first memory space and the second series of transactions are stored sequentially from a second end of the allocated first memory space opposite the first end.
2 . The method of claim 1 , wherein the first series of transaction stored sequentially from the first end are stored using consecutive memory transaction addresses counting in a first direction and the second series of transactions stored sequentially from the second end of the allocated first memory space are stored using consecutive memory transaction addresses counting opposite the first direction.
3 . The method of claim 1 , further comprising:
receiving a third series of memory access transactions from a third set of compressed data having a number of third transactions indeterminate in the transaction receiver;
receiving a fourth series of memory access transactions from a fourth set of compressed data having number of fourth transactions indeterminate in the transaction receiver;
receiving a count representing outstanding transactions for a combination of the third set of compressed data and the fourth set of compressed data or for a combination of the first set of compressed data, the second set of compressed data, the third set of compressed data, and the fourth set of compressed data in the transaction receiver; and
allocating a second memory space for the third series of transaction and the fourth series of transactions based at least in part on the received count representing outstanding transactions for the combination of the third set of compressed data and the fourth set of compressed data such that the third series of transactions are stored sequentially from a first end of the allocated second memory space and the fourth series of transactions are stored sequentially from a second end of the allocated second memory space opposite the first end.
4 . The method of claim 3 , further comprising allocating a partition in memory between the allocated first memory space for the first series of transactions and the second series of transactions and the allocated second memory space for the third series of transactions and the fourth series of transactions.
5 . The method of claim 1 , wherein a header comprising a part of at least one of the first series of transactions or the second series of transactions indicates the number of outstanding transactions for the combination of the first set of compressed data and the second set of compressed data.
6 . The method of claim 5 , wherein the number of outstanding transactions for the first set of compressed data is not derived from the number of outstanding transactions for the second set of compressed data.
7 . The method of claim 1 , wherein each of the first set of transactions and the second set of transactions comprises a compression element comprising a portion of a compressed data set.
8 . The method of claim 1 , wherein the transaction receiver comprises a memory controller.
9 . A device, comprising:
a memory transaction receiver circuit operable to:
receive a first series of memory access transactions from a first set of compressed data having a number of first transactions indeterminate in a transaction receiver;
receive a second series of memory access transactions from a second set of compressed data having a number of second transactions indeterminate in the transaction receiver; and
receive a count representing outstanding transactions for a combination of the first set of compressed data and the second set of compressed data in the transaction receiver; and
a memory allocation circuit operable to allocate a first memory space for the first series of transactions and the second series of transactions based at least in part on the received count representing outstanding transactions for the combination of the first set of compressed data and the second set of compressed data, and to store the first series of transactions sequentially from a first end of the allocated first memory space and to store the second series of transactions sequentially from a second end of the allocated first memory space opposite the first end.
10 . The device of claim 9 , wherein the first series of transaction stored sequentially from the first end are stored using consecutive memory transaction addresses counting in a first direction and the second series of transactions stored sequentially from the second end of the allocated first memory space are stored using consecutive memory transaction addresses counting opposite the first direction.
11 . The device of claim 9 , wherein:
the memory transaction receiver circuit is further operable to:
receive a third series of memory access transactions from a third set of compressed data having a number of third transactions indeterminate in the transaction receiver;
receive a fourth series of memory access transactions from a fourth set of compressed data having number of fourth transactions indeterminate in the transaction receiver; and
receive a count representing outstanding transactions for a combination of the third set of compressed data and the fourth set of compressed data or for a combination of the first set of compressed data, the second set of compressed data, the third set of compressed data, and the fourth set of compressed data in the transaction receiver; and
the memory allocation circuit is further operable to allocate a second memory space for the third series of transactions and the fourth series of transactions based at least in part on the received count representing outstanding transactions for the combination of the third set of compressed data and the fourth set of compressed data, and store the third series of transactions sequentially from a first end of the allocated second memory space and to store the fourth series of transactions sequentially from a second end of the allocated second memory space opposite the first end.
12 . The device of claim 11 , wherein the memory allocation circuit is further operable to allocate a partition in memory between the allocated first memory space for the first series of transactions and the second series of transactions and the allocated second memory space for the third series of transactions and the fourth series of transactions.
13 . The device of claim 9 , wherein the memory transaction receiver circuit is further operable to receive a header comprising a part of at least one of the first series of transactions or the second series of transactions that indicates the number of outstanding transactions for the combination of the first set of compressed data and the second set of compressed data.
14 . The device of claim 9 , wherein each of the first set of compressed data and the second set of transactions comprises a compression element comprising a portion of a compressed data set.
15 . The device of claim 9 , wherein the device comprises a memory controller.
16 . An article comprising a non-transitory computer-readable medium to store computer-readable hardware description language code for fabrication of a device, the device comprising:
a memory transaction receiver circuit operable to:
receive a first series of memory access transactions from a first set of compressed data having a number of first transactions indeterminate in a transaction receiver;
receive a second series of memory access transactions from a second set of compressed data having a number of second transactions indeterminate in the transaction receiver; and
receive a count representing outstanding transactions for a combination of the first set of compressed data and the second set of compressed data in the transaction receiver; and
a memory allocation circuit operable to:
allocate a first memory space for the first series of transactions and the second series of transactions based at least in part on the received count representing outstanding transactions for the combination of the first set of compressed data and the second set of compressed data; and
store the first series of transactions sequentially from a first end of the allocated first memory space and to store the second series of transactions sequentially from a second end of the allocated first memory space opposite the first end.
17 . The article of claim 16 , wherein the first series of transaction stored sequentially from the first end are stored using consecutive memory transaction addresses counting in a first direction and the second series of transactions stored sequentially from the second end of the allocated first memory space are stored using consecutive memory transaction addresses counting opposite the first direction.
18 . The article of claim 16 , the device further comprising:
memory transaction receiver circuitry further operable to:
receive a third series of memory access transactions from a third set of compressed data having a number of third transactions indeterminate in the transaction receiver;
receive a fourth series of memory access transactions from a fourth set of compressed data having number of fourth transactions indeterminate in the transaction receiver; and
receive a count representing outstanding transactions for a combination of the third set of compressed data and the fourth set of compressed data or for a combination of the first set of compressed data, the second set of compressed data, the third set of compressed data, and the fourth set of compressed data in the transaction receiver, wherein
memory allocation circuit is further operable to:
allocate a second memory space for the third series of transactions and the fourth series of transactions based at least in part on the received count representing outstanding transactions for the combination of the third set of compressed data and the fourth set of compressed data; and
store the third series of transactions sequentially from a first end of the allocated second memory space and to store the fourth series of transactions sequentially from a second end of the allocated second memory space opposite the first end.
19 . The article of claim 18 , wherein the memory allocation circuit is further operable to allocate a partition in memory between the allocated first memory space for the first series of transactions and the second series of transactions and the allocated second memory space for the third series of transactions and the fourth series of transactions.
20 . The article of claim 16 , wherein the device comprises a memory controller.