Bit-Flipping Algorithm for Binary Asymmetric Channels

1 . A method for decoding data read from a memory, comprising:

decoding with a memory controller the data read from the memory using symmetric bit-flip (BF) decoding and asymmetric BF decoding;

iterating the symmetric BF decoding;

during the iterating of the symmetric BF decoding, determining an asymmetric ratio of a) a number of errors in flipping from “0” to “1” to b) a number of errors in flipping from “1” to “0”; and

comparing the asymmetric ratio to an asymmetric ratio threshold in order to determine whether to continue the iterating of the symmetric BF decoding or to switch to the asymmetric BF decoding.

2 . The method of claim 1 , further comprising:

at an end of a first number of iterations of the symmetric BF decoding, when the asymmetric ratio is greater than the asymmetric ratio threshold, switching to the asymmetric BF decoding for decoding the data read from the memory device; and

at the end of the first number of iterations of the symmetric BF decoding, when the asymmetric ratio is less than the asymmetric ratio threshold, continuing the symmetric BF decoding for decoding the data read from the memory device.

3 . The method of claim 1 , further comprising automatically detecting the asymmetric ratio during the decoding.

4 . The method of claim 1 , further comprising determining hard decisions for bit flipping by comparing energy functions to a BF energy threshold.

5 . The method of claim 1 , further comprising:

determining whether an error rate for decoding with the symmetric BF decoding is larger than a correction capability of the symmetric BF decoding; and

utilizing the asymmetric BF decoding for decoding, when it is determined that the error rate is larger than the correction capability of the symmetric BF decoding.

6 . The method of claim 5 , further comprising: for the symmetric BF decoding

flipping a hard decision value when a first sum of neighboring check nodes in a parity check matrix and a channel mismatch is greater than a first threshold.

7 . The method of claim 6 , further comprising: for the asymmetric BF decoding,

flipping a hard decision value when a second sum of the neighboring check nodes in the parity check matrix and a weighted channel mismatch is greater than a second threshold.

8 . The method of claim 7 , further comprising

adapting decoder parameters based on the asymmetric ratio.

9 . The method of claim 8 , wherein the adapting comprises utilizing different values of weighting factors for the weighted channel mismatch depending on a magnitude on the asymmetric ratio.

10 . The method of claim 8 , wherein the adapting comprises utilizing different values for the first and second thresholds depending on a magnitude on the asymmetric ratio.

11 . A memory system comprising:

a memory device; and

a controller in communication with the memory device, and configured to:

decode the data read from the memory using symmetric bit-flip (BF) decoding and asymmetric BF decoding;

iterate the symmetric BF decoding;

during the iterating of the symmetric BF decoding, determine an asymmetric ratio of a) a number of errors in flipping from “0” to “1” to b) a number of errors in flipping from “1” to “0”; and

compare the asymmetric ratio to an asymmetric ratio threshold in order to determine whether to continue the iterating of the symmetric BF decoding or to switch to the asymmetric BF decoding.

12 . The memory system of claim 11 , wherein the controller is configured to:

at an end of a first number of iterations of the symmetric BF decoding and when the asymmetric ratio is greater than the asymmetric ratio threshold, switch to the asymmetric BF decoding for decoding the data read from the memory device; and

at the end of the first number of iterations of the symmetric BF decoding, if the asymmetric ratio is less than the asymmetric ratio threshold, continue symmetric BF decoding for decoding the data read from the memory device.

13 . The memory system of claim 12 , wherein the controller is configured to automatically detect the asymmetric ratio during the decoding.

14 . The memory system of claim 12 , wherein the controller is configured to determine hard decisions for bit flipping by comparing energy functions to a BF energy threshold.

15 . The memory system of claim 11 , wherein the controller is configured to determine whether an error rate for decoding with the symmetric BF decoding is larger than a correction capability of the symmetric BF decoding; and

utilize the asymmetric BF decoding for decoding, when it is determined that the error rate is larger than the correction capability of the symmetric BF decoding.

16 . The memory system of claim 15 , wherein the controller is configured to, for the symmetric BF decoding, flip a hard decision value when a first sum of neighboring check nodes in a parity check matrix and a channel mismatch is greater than a first threshold.

17 . The memory system of claim 15 , wherein the controller is configured to, for the asymmetric BF decoding, flip a hard decision value when a second sum of the neighboring check nodes in the parity check matrix and a weighted channel mismatch is greater than a second threshold.

18 . The memory system of claim 15 , wherein the controller is configured to adapt decoder parameters based on the asymmetric ratio.

19 . The memory system of claim 18 , wherein the controller is configured to utilize different values of weighting factors for the weighted channel mismatch depending on a magnitude on the asymmetric ratio.

20 . The memory system of claim 18 , wherein the controller is configured to utilize different values for the first and second thresholds depending on a magnitude on the asymmetric ratio.