CONVERTING PROCESSING DIMENSIONS OF A WAFER PACKAGE
The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve producing or manufacturing wafers having circuit packages formed thereon. Techniques described herein related to modifying a dimension of wafers in order that the wafers conform to a nominal dimension, such that the wafers may be implemented in connection with processing equipment that is specifically configured to operate on wafers of the nominal dimension.
1 . A method of modifying a base dimension of a wafer structure, comprising;
obtaining a photonic integrated circuit (PIC) wafer having a first base dimension, the PIC wafer comprising:
a region near a top surface of the PIC wafer designed to allow light to enter and exit the PIC wafer;
optical transmitter and receiver portions in optical communication with the region, the optical transmitter and receiver portions having electrical interconnects to the top surface of the PIC wafer in a portion that does not extend into the region;
disposing one or more electronic components on the PIC wafer, the one or more electronic components including electrical transmitter and receiver portions interconnected with the optical transmitter and receiver portions via electrical interconnects, forming electro-optical paths to and from the one or more electronic components to region;
positioning the PIC wafer over a base plate having a second base dimension that is larger than the first base dimension, wherein the PIC wafer covers only a portion of a top surface of the base plate such that a peripheral portion of the top surface of the base plate is exposed around a perimeter of the PIC wafer; and
depositing a peripheral overmold over the PIC wafer, the one or more electronic components, and the exposed portion of the base plate around the perimeter of the PIC wafer to form a molded wafer package having the second base dimension.
2 . The method of claim 1 , further comprising removing the base plate from the molded wafer package such that the molded wafer package, after removal from the base plate, has the second base dimension.
3 . The method of claim 1 , further comprising removing a layer of the molded wafer package to expose the one or more electronic components disposed on the wafer.
4 . The method of claim 3 , wherein removing the layer of the molded wafer package exposes an optical path to a grating coupler region of the plurality of grating coupler regions near the top surface of the PIC wafer.
5 . The method of claim 4 , further comprising coupling an optical fiber to a grating coupler in the region using an optical interface component.
6 . The method of claim 5 , wherein the optical interface component is a fiber array unit (FAU).
7 . The method of claim 1 , further comprising performing processing tasks on the molded wafer package using processing equipment configured to process components on a wafer structure having the second base dimension.
8 . The method of claim 7 , wherein the processing tasks include forming through-silicon vias (TSVs) in the PIC wafer and forming interconnects on the PIC wafer connected to the TSVs for providing electrical power to the one or more electronic components.
9 . The method of claim 1 , wherein a shape of the first base dimension is a circle having a diameter of approximately eight inches.
10 . The method of claim 9 , wherein the second base dimension is a circle having a diameter of approximately twelve inches such that the molded wafer package is a circular wafer package having a base dimension of approximately twelve inches.
11 . The method of claim 1 , wherein the PIC wafer comprises waveguides formed within the PIC wafer and passing between the region and the optical transmitter and received portions.
12 . The method of claim 1 , wherein the PIC wafer comprises bumps on the top surface of the PIC wafer coupling one or more components within the PIC to the one or more electronic components disposed on the top surface of the PIC wafer.
13 . A method of modifying a base dimension of a wafer structure, comprising:
obtaining a wafer package having a first base dimension and comprising:
a wafer having the first base dimension and having a plurality of first electrical connections on a top surface of the wafer; and
one or more electronic components having a plurality of second electrical connections on a bottom surface thereof, and being positioned on the top surface of the wafer such that there are electrical couplings between the plurality of first electrical connections and the plurality of second electrical connections;
positioning the wafer package over a base plate having a second base dimension that is larger than the first base dimension, wherein the wafer package covers only a portion of a top surface of the base plate such that a peripheral portion of the top surface of the base plate is exposed around a perimeter of the wafer package; and
depositing a peripheral overmold over the wafer, the one or more electronic components, and the exposed portion of the base plate around the perimeter of the wafer package to form a molded wafer package having the second base dimension.
14 . The method of claim 13 , further comprising removing the base plate from the molded wafer package such that the molded wafer package, after removal from the base plate, has the second base dimension.
15 . The method of claim 13 , further comprising removing a layer of the molded wafer package to expose the one or more electronic components disposed on the wafer.
16 . The method of claim 15 , wherein removing the layer includes forming a planar surface of the molded wafer package.
17 . The method of claim 13 , further comprising performing processing tasks on the molded wafer package using processing equipment configured to process components on a wafer structure having the second base dimension.
18 . The method of claim 17 , wherein the processing tasks include forming through-silicon vias (TSVs) in the wafer and forming interconnects on the wafer connected to the TSVs for providing electrical power to the one or more electronic components.
19 . The method of claim 13 , wherein a shape of the first base dimension is a circle having a diameter of approximately eight inches.
20 . The method of claim 17 , wherein the second base dimension is a circle having a diameter of approximately twelve inches such that the molded wafer package is a circular wafer package having a base dimension of approximately twelve inches.
21 . The method of claim 13 , wherein the one or more electronic components includes one or more electrical integrated circuit dies, memory dies, and other electrical components capable of communicating, processing, or storing data.
22 . A method of modifying a base dimension of a wafer structure, comprising:
obtaining a wafer package having a first base dimension and comprising:
a wafer having a first base dimension and having a plurality of first electrical connections on a top surface of the wafer; and
one or more electronic components having a plurality of second electrical connections on a bottom surface thereof, and being positioned on the top surface of the wafer such that there are electrical couplings between the plurality of first electrical connections and the plurality of second electrical connections;
positioning the wafer package within a peripheral wafer having a second base dimension that is larger than the first base dimension, wherein peripheral wafer includes a cutout, the cutout having a size and shape corresponding to the first base dimension such that the wafer package fits within the cutout;
depositing a peripheral overmold over at least a cutout portion of the peripheral wafer such that the overmold is deposited over the wafer and the one or more electronic components, wherein the overmold connects the wafer and the peripheral wafer to form the molded wafer package having the second base dimension.
23 . The method of claim 22 , wherein the cutout is a circular cutout, and wherein the wafer fits within the cutout such that the top surface of the wafer aligns approximately with a top surface of the peripheral wafer.
24 . The method of claim 22 , wherein the peripheral wafer is thicker than the wafer such that the top surface of the wafer is below a top surface of the peripheral wafer.
25 . The method of claim 22 , wherein the wafer is circular and the first base dimension is a diameter of approximately eight inches.
26 . The method of claim 25 , wherein the second base dimension has a diameter of approximately twelve inches.
27 . The method of claim 22 , further comprising performing processing tasks on the molded wafer package using processing equipment configured to process components on a wafer structure having the second base dimension.