PRESERVING ACCESS TO OPTICAL COMPONENTS ON A WAFER PACKAGE WITH SACRIFICIAL DIE
The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve techniques for packaging an electro-photonic circuit while preserving access to a grating coupler, which may involve using a sacrificial die in conjunction with a unique overmolding process.
1 . A method for packaging an electro-photonic circuit, comprising:
obtaining a wafer having a region designed to allow light to exit or enter from a top surface of the wafer;
positioning a sacrificial die over the top surface of the wafer covering the region, wherein the sacrificial die comprises a pre-cut portion;
depositing an overmold over the wafer and over the sacrificial die;
grinding down a top surface of the overmold, wherein grinding down the top surface of the overmold includes grinding down from a top surface of the sacrificial die to at least the pre-cut portion of the sacrificial die and causing the pre-cut portion of the sacrificial die to disconnect from a body of the sacrificial die; and
removing the pre-cut portion of the sacrificial die that disconnected from the body of the sacrificial die.
2 . The method of claim 1 , wherein removing the pre-cut portion of the sacrificial die exposes an optical path to the region near the top surface of the wafer.
3 . The method of claim 1 , further comprising coupling a plurality of optical fibers to the region using an optical interface component.
4 . The method of claim 3 , wherein the optical interface component is a fiber array unit (FAU).
5 . The method of claim 4 , wherein the FAU and the optical interface couple components of the electro-photonic circuit with one or more additional components off-chip from the electro-photonic circuit.
6 . The method of claim 1 , further comprising, prior to depositing the overmold over the top surface of the wafer, disposing one or more electronic components on the top surface of the wafer, wherein disposing the one or more of electronic components over the top surface of the wafer comprises connecting electrical contacts on the one or more electronic components to bumps on the top surface of the wafer and forming electro-optical paths to and from the one or more electronic components to the region via waveguides formed within the wafer.
7 . The method of claim 6 , wherein the one or more electronic components include one or more of a processor component, a memory component, or an analog mixed signal (AMS) block.
8 . The method of claim 1 , further comprising pre-cutting the sacrificial die by cutting through a portion of the body of the sacrificial die without cutting through an entire body of the sacrificial die.
9 . The method of claim 1 , wherein an uncut portion of the body of the sacrificial die is between 25 and 75 microns thick.
10 . The method of claim 9 , wherein the body of the sacrificial die prior to grinding down from the top surface of the sacrificial die is less than 1000 microns thick.
11 . The method of claim 1 , wherein the sacrificial die includes a protective layer that, when positioned over the top surface of the wafer at the position corresponding to the region, provides a protective barrier between the pre-cut portion of the sacrificial die and the region.
12 . The method of claim 1 , wherein the sacrificial die includes an adhesive layer around a perimeter of a bottom surface of the pre-cut portion of the sacrificial die, wherein the adhesive layer secures the sacrificial die in place over the top surface of the wafer at the position corresponding to the region.
13 . The method of claim 1 , wherein the overmold does not flow between the sacrificial die and the wafer.
14 . The method of claim 1 , wherein the sacrificial die is an electrically non-functional component.
15 . A method for packaging an electro-photonic circuit, comprising:
obtaining a photonic integrated circuit (PIC) wafer comprising:
a region near a top surface of the PIC wafer designed to allow light to enter and exit the PIC wafer; and
optical transmitter and receiver portions in optical communication with the region, the optical transmitter and receiver portions having electrical interconnects to the top surface of the PIC wafer in a portion that does not extend into the region;
disposing one or more electronic components on the PIC wafer, the one or more electronic components including electrical transmitter and receiver portions interconnected with the optical transmitter and receiver portions and forming electro-optical paths to and from the one or more electronic components to the region;
positioning a sacrificial die over the top surface of the PIC wafer covering the region, wherein the sacrificial die comprises a pre-cut portion;
depositing an overmold over the PIC wafer, the one or more electronic components, and over the sacrificial die;
grinding down a top surface of the overmold, wherein grinding down the top surface of the overmold includes grinding down from a top surface of the sacrificial die to at least the pre-cut portion of the sacrificial die and causing the pre-cut portion of the sacrificial die to disconnect from a body of the sacrificial die; and
removing the pre-cut portion of the sacrificial die that disconnected from the body of the sacrificial die.
16 . The method of claim 15 , wherein removing the pre-cut portion of the sacrificial die exposes an optical path to the region near the top surface of the PIC wafer.
17 . The method of claim 15 , further comprising coupling an optical fiber to a grating coupler in the region using an optical interface component.
18 . The method of claim 17 , wherein the optical interface component is a fiber array unit (FAU).
19 . The method of claim 18 , wherein the FAU optically couples components of the electro-photonic circuit with one or more additional components off-chip from the electro-photonic circuit via waveguides formed in the PIC wafer.
20 . The method of claim 15 , further comprising pre-cutting the sacrificial die by cutting through a portion of the body of the sacrificial die without cutting through an entire body of the sacrificial die.
21 . The method of claim 15 , wherein an uncut portion of the body of the sacrificial die is between 25 and 75 microns thick.
22 . The method of claim 21 , wherein the body of the sacrificial die prior to grinding down from the top surface of the sacrificial die is less than 1000 microns thick.
23 . The method of claim 15 , wherein the sacrificial die includes a protective layer that, when positioned over the top surface of the wafer at the position corresponding to the region, provides a protective barrier between the pre-cut portion of the sacrificial die and the region.
24 . The method of claim 15 , wherein the sacrificial die includes an adhesive layer around a perimeter of a bottom surface of the pre-cut portion of the sacrificial die, wherein the adhesive layer secures the sacrificial die in place over the top surface of the PIC wafer at the position corresponding to the region.
25 . The method of claim 15 , wherein the overmold does not flow between the sacrificial die and the PIC wafer.
26 . The method of claim 15 , wherein the sacrificial die is an electrically non-functional component.