Pixel of a display device and display device
A pixel of a display device includes a first transistor including a gate connected to a gate node, a first terminal connected to a drain node, and a second terminal connected to a source node, a second transistor configured to transfer a first power supply voltage to the gate node in response to an initialization signal, a third transistor configured to diode-connect the first transistor in response to a write signal, a fourth transistor configured to transfer a second power supply voltage to the source node in response to the write signal, a fifth transistor configured to transfer the first power supply voltage to the drain node in response to an emission signal, a capacitor including a first electrode connected to a data line, and a second electrode connected to the gate node, and a light emitting element including an anode connected to the source node, and a cathode which receives the second power supply voltage.
1 . A pixel of a display device, the pixel comprising:
a first transistor including a gate connected to a gate node, a first terminal connected to a drain node, and a second terminal connected to a source node;
a second transistor configured to transfer a first power supply voltage to the gate node in response to an initialization signal;
a third transistor configured to diode-connect the first transistor in response to a write signal;
a fourth transistor configured to transfer a second power supply voltage to the source node in response to the write signal;
a fifth transistor configured to transfer the first power supply voltage to the drain node in response to an emission signal;
a capacitor including a first electrode connected to a data line, and a second electrode connected to the gate node; and
a light emitting element including an anode connected to the source node, and a cathode which receives the second power supply voltage.
2 . The pixel of claim 1 , wherein, when the write signal has a high level, the fourth transistor transfers the second power supply voltage to the source node, the third transistor connects the gate node and the drain node to each other, and the gate node has a voltage corresponding to a sum of the second power supply voltage and a threshold voltage of the first transistor.
3 . The pixel of claim 2 , wherein, when the write signal has the high level, a data voltage is applied to the first electrode of the capacitor through the data line.
4 . The pixel of claim 3 , wherein, when the emission signal has the high level, an emission voltage higher than the data voltage is applied to the first electrode of the capacitor through the data line.
5 . The pixel of claim 1 , wherein the second transistor includes a gate which receives the initialization signal, a first terminal which receives the first power supply voltage, and a second terminal connected to the gate node,
wherein the third transistor includes a gate which receives the write signal, a first terminal connected to the gate node, and a second terminal connected to the drain node,
wherein the fourth transistor includes a gate which receives the write signal, a first terminal connected to the source node, and a second terminal which receives the second power supply voltage, and
wherein the fifth transistor includes a gate which receives the emission signal, a first terminal which receives the first power supply voltage, and a second terminal connected to the drain node.
6 . The pixel of claim 1 , wherein the first through fifth transistors are N-type metal oxide semiconductor (NMOS) transistors.
7 . The pixel of claim 1 , wherein the initialization signal is substantially simultaneously applied to a plurality of pixels of the display device,
wherein the write signal is sequentially applied to the plurality of pixels on a row-by-row basis, and
wherein the emission signal is substantially simultaneously applied to the plurality of pixels.
8 . The pixel of claim 1 , wherein a frame period for the display device includes:
an initialization period in which the gate node is initialized;
a data writing and compensation period in which a data voltage is provided through the data line and a threshold voltage compensation operation is performed in a diode connection method; and
an emission period in which the light emitting element emits light.
9 . The pixel of claim 8 , wherein, during the initialization period,
the initialization signal has a high level, the write signal and the emission signal have a low level, an emission voltage is provided through the data line,
the second transistor transfers the first power supply voltage to the gate node in response to the initialization signal having the high level, and
the gate node is initialized based on the first power supply voltage.
10 . The pixel of claim 8 , wherein, during the data writing and compensation period,
the write signal has a high level, the initialization signal and the emission signal have a low level, the data voltage is provided through the data line,
the fourth transistor transfers the second power supply voltage to the source node in response to the write signal having the high level,
the third transistor diode-connects the first transistor in response to the write signal having the high level,
a voltage of the gate node is changed from the first power supply voltage to a voltage corresponding to a sum of the second power supply voltage and a threshold voltage of the first transistor, and
the data voltage is applied to the first electrode of the capacitor through the data line.
11 . The pixel of claim 8 , wherein, during the emission period,
the emission signal has a high level, the initialization signal and the write signal have a low level, an emission voltage is provided through the data line,
the fifth transistor is turned on in response to the emission signal having the high level,
the emission voltage higher than the data voltage is applied to the first electrode of the capacitor through the data line,
the first transistor generates a driving current based on a voltage of the gate node, and
the light emitting element emits light based on the driving current.
12 . The pixel of claim 1 , further comprising:
a sixth transistor disposed between the data line and the first electrode of the capacitor, and configured to connect the data line to the first electrode of the capacitor in response to the write signal;
a seventh transistor configured to transfer the first power supply voltage to the first electrode of the capacitor in response to the initialization signal; and
an eighth transistor configured to transfer the first power supply voltage to the first electrode of the capacitor in response to the emission signal.
13 . The pixel of claim 12 , wherein the sixth transistor includes a gate which receives the write signal, a first terminal connected to the first electrode of the capacitor, and a second terminal connected to the data line,
wherein the seventh transistor includes a gate which receives the initialization signal, a first terminal which receives the first power supply voltage, and a second terminal connected to the first electrode of the capacitor, and
wherein the eighth transistor includes a gate which receives the emission signal, a first terminal which receives the first power supply voltage, and a second terminal connected to the first electrode of the capacitor.
14 . The pixel of claim 12 , wherein the first through eighth transistors are NMOS transistors.
15 . The pixel of claim 12 , wherein the initialization signal, the write signal and the emission signal are sequentially applied to a plurality of pixels of the display device on a row-by-row basis.
16 . A pixel of a display device, the pixel comprising:
a first transistor including a gate connected to a gate node, a first terminal connected to a drain node, and a second terminal connected to a source node;
a second transistor including a gate which receives an initialization signal, a first terminal which receives a first power supply voltage, and a second terminal connected to the gate node;
a third transistor including a gate which receives a write signal, a first terminal connected to the gate node, and a second terminal connected to the drain node;
a fourth transistor including a gate which receives the write signal, a first terminal connected to the source node, and a second terminal which receives a second power supply voltage;
a fifth transistor including a gate which receives an emission signal, a first terminal which receives the first power supply voltage, and a second terminal connected to the drain node;
a capacitor including a first electrode connected to a data line, and a second electrode connected to the gate node; and
a light emitting element including an anode connected to the source node, and a cathode which receives the second power supply voltage.
17 . The pixel of claim 16 , wherein the initialization signal is substantially simultaneously applied to a plurality of pixels of the display device,
wherein the write signal is sequentially applied to the plurality of pixels on a row-by-row basis, and
wherein the emission signal is substantially simultaneously applied to the plurality of pixels.
18 . The pixel of claim 16 , further comprising:
a sixth transistor disposed between the data line and the first electrode of the capacitor, and including a gate which receives the write signal, a first terminal connected to the first electrode of the capacitor, and a second terminal connected to the data line;
a seventh transistor including a gate which receives the initialization signal, a first terminal which receives the first power supply voltage, and a second terminal connected to the first electrode of the capacitor; and
an eighth transistor including a gate which receives the emission signal, a first terminal which receives the first power supply voltage, and a second terminal connected to the first electrode of the capacitor.
19 . The pixel of claim 18 , wherein the initialization signal, the write signal and the emission signal are sequentially applied to a plurality of pixels of the display device on a row-by-row basis.
20 . An electronic device comprising:
a processor configured to provide input image data; and
a display device configured to receive the input image data from the processor, and to display an image based on the input image data,
wherein the display device includes:
a display panel including a plurality of pixels;
a data driver configured to provide a data voltage to each of the plurality of pixels;
a scan driver configured to provide an initialization signal and a write signal to each of the plurality of pixels;
an emission driver configured to provide an emission signal to each of the plurality of pixels; and
a controller configured to control the data driver, the scan driver and the emission driver, and
wherein each of the plurality of pixels includes:
a first transistor including a gate connected to a gate node, a first terminal connected to a drain node, and a second terminal connected to a source node;
a second transistor configured to transfer a first power supply voltage to the gate node in response to the initialization signal;
a third transistor configured to diode-connect the first transistor in response to the write signal;
a fourth transistor configured to transfer a second power supply voltage to the source node in response to the write signal;
a fifth transistor configured to transfer the first power supply voltage to the drain node in response to the emission signal;
a capacitor including a first electrode connected to a data line, and a second electrode connected to the gate node; and
a light emitting element including an anode connected to the source node, and a cathode which receives the second power supply voltage.