PROCESSOR WITH DELAYED INSTRUCTION PIPELINE FLUSH
In a general aspect, a processor includes a plurality of control registers, an instruction processing pipeline operationally coupled with the control registers, and a pipeline flush control unit operationally coupled with the instruction processing pipeline. The pipeline flush control unit is configured to record, in response to the instruction processing pipeline completing execution of a first instruction, an indication of the first instruction. The first instruction is configured to write to a first control register of the control registers. The pipeline flush control unit is also configured to identify a second instruction in the instruction processing pipeline prior to completing execution of the second instruction, and determine, based on a set of predetermined criteria, whether the second instruction conflicts with the first instruction. If the second instruction is determined to conflict with the first instruction, the pipeline flush control unit initiates flushing of the instruction processing pipeline.
1 . A processor comprising:
a plurality of control registers;
an instruction processing pipeline operationally coupled with the plurality of control registers, the instruction processing pipeline being configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of control registers; and
a pipeline flush control unit operationally coupled with the instruction processing pipeline, the pipeline flush control unit being configured to:
record, in response to the instruction processing pipeline completing execution of a first instruction, an indication of the first instruction, the first instruction being configured to write to a first control register of the plurality of control registers;
identify a second instruction in the instruction processing pipeline prior to completing execution of the second instruction;
determine, based on a set of predetermined criteria, whether the second instruction conflicts with the first instruction; and
if the second instruction is determined to conflict with the first instruction, initiate flushing of the instruction processing pipeline.
2 . The processor of claim 1 , wherein, if the second instruction is determined not to conflict with the first instruction, the instruction processing pipeline is configured to complete execution of the second instruction.
3 . The processor of claim 1 , wherein the second instruction is configured to write to a second control register of the plurality of control registers,
the pipeline flush control unit being further configured to:
record an indication of the second instruction;
identify a third instruction in the instruction processing pipeline prior to completing execution of the third instruction;
determine, based on the set of predetermined criteria, whether the third instruction conflicts with the first instruction or conflicts with the second instruction; and
if the third instruction is determined to conflict with the first instruction or the second instruction, initiate flushing of the instruction processing pipeline.
4 . The processor of claim 3 , wherein, if the third instruction is determined not to conflict with the first instruction or the second instruction, the instruction processing pipeline is further configured to complete execution of the third instruction.
5 . The processor of claim 1 , wherein the pipeline flush control unit includes an accumulator configured to store the indication of the first instruction and the indication of the second instruction.
6 . The processor of claim 1 , wherein the processor is configured to clear the accumulator in response to initiating flushing of the instruction processing pipeline.
7 . The processor of claim 1 , wherein the instruction processing pipeline includes, sequentially:
a fetch stage;
a decode stage;
an execute stage;
a memory stage; and
a writeback stage.
8 . The processor of claim 1 , wherein the instruction processing pipeline includes a RISC-V instruction processing pipeline.
9 . A processor comprising:
a plurality of control registers (CRs);
an instruction processing pipeline operationally coupled with the plurality of CRs, the instruction processing pipeline being configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of CRs, the plurality of machine-readable instructions including a plurality of CR instructions and a plurality of non-CR instructions; and
a pipeline flush control unit operationally coupled with the instruction processing pipeline, the pipeline flush control unit being configured to:
record, in response to the instruction processing pipeline completing execution of a first instruction, an indication of the first instruction, the first instruction being a first CR instruction of the plurality of CR instructions;
identify a second instruction in the instruction processing pipeline prior to completing execution of the second instruction;
determine, based on a set of predetermined criteria, whether the second instruction conflicts with the first CR instruction; and
if the second instruction is determined to conflict with the first CR instruction, initiate flushing of the instruction processing pipeline.
10 . The processor of claim 9 , wherein, if the second instruction is determined not to conflict with the first instruction, the instruction processing pipeline is configured to complete execution of the second instruction.
11 . The processor of claim 9 , wherein the second instruction is a non-CR instruction of the plurality of non-CR instructions.
12 . The processor of claim 9 , wherein the second instruction is a second CR instruction of the plurality of CR instructions,
the pipeline flush control unit being further configured to:
record an indication of the second CR instruction;
identify a third instruction in the instruction processing pipeline prior to completing execution of the third instruction;
determine, based on the set of predetermined criteria, whether the third instruction conflicts with the first CR instruction or the second CR instruction; and
if the third instruction is determined to conflict with the first CR instruction or the second CR instruction, initiate flushing of the instruction processing pipeline.
13 . The processor of claim 12 , wherein, if the third instruction is determined not to conflict with the first CR instruction or the second instruction, the instruction processing pipeline is further configured to complete execution of the third instruction.
14 . The processor of claim 12 , where the third instruction is a non-CR instruction.
15 . The processor of claim 9 , wherein the pipeline flush control unit includes an accumulator configured to store the indication of the first CR instruction and the indication of the second CR instruction.
16 . The processor of claim 9 , wherein the processor is configured to clear the accumulator in response to initiating flushing of the instruction processing pipeline.
17 . The processor of claim 9 , wherein the instruction processing pipeline includes a RISC-V instruction processing pipeline.
18 . A method of processing machine-readable instructions, the method comprising:
completing, in an instruction processing pipeline of a processor, execution of a first instruction of the machine-readable instructions;
determining, by the processor in response to completing the execution of the first instruction, that flushing of the instruction processing pipeline can be delayed;
recording an indication of the first instruction;
examining the instruction processing pipeline to identify a second instruction of the machine-readable instructions in the instruction processing pipeline prior to completing execution of the second instruction;
determining, based on a set of predetermined criteria, whether the second instruction conflicts with the first instruction; and
if the second instruction is determined to conflict with the first instruction, initiating flushing of the instruction processing pipeline.
19 . The method of claim 18 , wherein:
the first instruction is a control register (CR) instruction; and
the second instruction is a non-CR instruction.
20 . The method of claim 18 , wherein, if the second instruction is determined not to conflict with the first instruction, the method further comprises completing execution of the second instruction.
21 . The method of claim 18 , wherein:
the first instruction is a first control register (CR) instruction; and
the second instruction is a second CR instruction,
the method further comprising:
recording an indication of the second CR instruction;
identifying a third instruction of the machine-readable instructions in the instruction processing pipeline prior to completing execution of the third instruction;
determining, based on the set of predetermined criteria, whether the third instruction conflicts with the first CR instruction or conflicts with the second CR instruction; and
if the third instruction is determined to conflict with the first CR instruction or the second CR instruction, initiating flushing of the instruction processing pipeline.
22 . The method of claim 21 , wherein the third instruction is a non-CR instruction.
23 . The method of claim 21 , wherein, if the third instruction is determined not to conflict with the first CR instruction or the second CR instruction, the method further comprises completing execution of the third instruction.
24 . A processor comprising:
a plurality of control registers;
an instruction processing pipeline operationally coupled with the plurality of control registers, the instruction processing pipeline being configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of control registers; and
a pipeline flush control unit operationally coupled with the instruction processing pipeline, the pipeline flush control unit and the instruction processing pipeline being configured to:
record, in response to the instruction processing pipeline completing execution of a first instruction, an indication of the first instruction, the first instruction being configured to write to a first control register of the plurality of control registers;
identify a second instruction in the instruction processing pipeline prior to completing execution of the second instruction;
determine, based on a set of predetermined criteria, that the second instruction does not conflict with the first instruction;
complete execution of the second instruction;
identify a third instruction in the instruction processing pipeline;
determine, based on the set of predetermined criteria, that the third instruction conflicts with the first instruction; and
in response to the determination that the third instruction conflicts with the first instruction, initiate flushing of the instruction processing pipeline prior to completing execution of the third instruction.