PRESERVING ACCESS TO OPTICAL COMPONENTS ON A WAFER PACKAGE WITH SACRIFICIAL CAP
The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve techniques for packaging an electro-photonic circuit while preserving access to a grating coupler, which may involve using a sacrificial cap in conjunction with a unique overmolding process.
1 . A method for packaging an electro-photonic circuit, comprising:
obtaining a wafer having a region designed to allow light to exit or enter from a top surface of the wafer;
positioning a sacrificial cap over the top surface of the wafer covering the region, wherein the sacrificial cap includes a recess formed therein, and wherein the recess is positioned over a portion of the region when the sacrificial cap is placed over the top surface of the wafer;
depositing an overmold over the wafer and over the sacrificial cap; and
grinding down a top surface of the overmold, wherein grinding down the top surface of the overmold includes grinding down from a top portion of the sacrificial cap to expose an opening at a top of the recess positioned over the portion of the region.
2 . The method of claim 1 , wherein exposing the opening to the recess exposes an optical path to the region near the top surface of the wafer.
3 . The method of claim 1 , further comprising coupling a plurality of optical fibers to the region using an optical interface component.
4 . The method of claim 3 , wherein the optical interface component is a fiber array unit (FAU).
5 . The method of claim 4 , wherein the FAU and the optical interface component couple components of the electro-photonic circuit with one or more additional components off-chip from the electro-photonic circuit.
6 . The method of claim 1 , further comprising, prior to depositing the overmold over the top surface of the wafer, disposing one or more electronic components on the top surface of the wafer, wherein disposing the one or more of electronic components over the top surface of the wafer comprises connecting electrical contacts on the one or more electronic components to bumps on the top surface of the wafer and forming electro-optical paths to and from the one or more electronic components to the region via waveguides formed within the wafer.
7 . The method of claim 6 , wherein the one or more electronic components include one or more of a processor component, a memory component, or an analog mixed signal (AMS) block.
8 . The method of claim 1 , wherein, prior to grinding down the top surface of the overmold, the top portion of the sacrificial cap extends over a top of the recess, and wherein the top portion of the sacrificial cap has a thickness of greater than 25 microns.
9 . The method of claim 1 , wherein a thickness between a top and bottom surface of the sacrificial cap prior to grinding down the top surface of the overmold is less than 1000 microns.
10 . The method of claim 1 , wherein the overmold does not flow between the sacrificial cap and the wafer.
11 . The method of claim 1 , wherein the sacrificial cap is made from a same overmolding material as the overmold that is deposited over the wafer.
12 . The method of claim 1 , wherein the sacrificial cap is made from a different overmolding material as the overmold that is deposited over the wafer.
13 . A method for packaging an electro-photonic circuit, comprising:
obtaining a photonic integrated circuit (PIC) wafer comprising:
a region near a top surface of the PIC wafer designed to allow light to enter and exit the PIC wafer; and
optical transmitter and receiver portions in optical communication with the region, the optical transmitter and receiver portions having electrical interconnects to the top surface of the PIC wafer in a portion that does not extend into the region;
disposing one or more electronic components on the PIC wafer, the one or more electronic components including electrical transmitter and receiver portions interconnected with the optical transmitter and receiver portions and forming electro-optical paths to and from the one or more electronic components to the region;
positioning a sacrificial cap over the top surface of the PIC wafer covering the region, wherein the sacrificial cap includes a recess formed therein, and wherein the recess is positioned over a portion of the region when the sacrificial cap is placed over the top surface of the PIC wafer;
depositing an overmold over the PIC wafer, the one or more electronic components, and the sacrificial cap; and
grinding down a top surface of the overmold, wherein grinding down the top surface of the overmold includes grinding down from a top portion of the sacrificial cap to create an opening at a top of the recess positioned over the portion of the region.
14 . The method of claim 13 , wherein exposing the opening at the top of the recess exposes an optical path to the region near the top surface of the PIC wafer.
15 . The method of claim 13 , further comprising coupling an optical fiber to a grating coupler in the region using an optical interface component.
16 . The method of claim 15 , wherein the optical interface component is a fiber array unit (FAU).
17 . The method of claim 16 , wherein the FAU optically couples components of the electro-photonic circuit with one or more additional components off-chip from the electro-photonic circuit via waveguides formed in the PIC wafer.
18 . The method of claim 13 , further comprising, prior to depositing the overmold over the top surface of the PIC wafer, disposing one or more electronic components on the top surface of the PIC wafer, wherein disposing the plurality of electronic components over the top surface of the PIC wafer comprises connecting electrical contacts on the electronic components to bumps on the top surface of the PIC wafer and forming electro-optical paths to and from the plurality of electronic components to the plurality of grating coupler regions via waveguides formed within the PIC wafer.
19 . The method of claim 18 , wherein the one or more electronic components include one or more of a processor component, a memory component, or an analog mixed signal (AMS) block.
20 . The method of claim 13 , wherein, prior to grinding down the top surface of the overmold, the top portion of the sacrificial cap extends over the top of the recess, and wherein the top portion of the sacrificial cap has a thickness of greater than 25 microns.
21 . The method of claim 13 , wherein a thickness between a top and bottom surface of the sacrificial cap prior to grinding down the top surface of the overmold is less than 1000 microns.
22 . The method of claim 13 , wherein the overmold does not flow between the sacrificial cap and the PIC wafer.
23 . The method of claim 13 , wherein the sacrificial cap is made from a same overmolding material as the overmold that is deposited over the PIC wafer.
24 . The method of claim 13 , wherein the sacrificial cap is made from a different overmolding material as the overmold that is deposited over the wafer.