IP Library Granted Patent US 12,732,165
Granted Patent B1
US 12,732,165 · App. 19/172,268 · Granted Sep 8, 2026

Clock generator with dual-path temperature compensation

Inventors: Saleh Heidary Shalmany (Delft, NL); Kamran Souri (The Hague, NL); Sassan Tabatabaei (Sunnyvale, CA); Uǧur Sönmez (The Hague, NL)
Assignee: SiTime Corporation
H03K3/011G06F1/04
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Quick Facts
Patent No.
US 12,732,165
App. No.
19/172,268
Granted
Sep 8, 2026
Kind
B1
Abstract

In a timing signal generator having a resonator, one or more temperature-sense circuits generate an analog temperature signal and a digital temperature signal indicative of temperature of the resonator. First and second temperature compensation signal generators to generate, respectively, an analog temperature compensation signal according to the analog temperature signal and a digital temperature compensation signal according to the digital temperature signal. Clock generating circuitry drives the resonator into mechanically resonant motion and generates a temperature-compensated output timing signal based on the mechanically resonant motion, the analog temperature compensation signal and the digital temperature compensation signal.

Claims (71)

1 . A multi-die integrated circuit comprising:

a first die having thereon a microelectromechanical systems (MEMS) resonator, wherein the MEMS resonator has a stiffness that is characterized by a temperature-dependent variation;

a circuits' die having circuitry to receive a first signal, the first signal representing a frequency of vibration of the MEMS resonator, and to generate therefrom an oscillation signal for output by the multi-die integrated circuit;

wherein the circuitry is further operable to:

receive a second signal representing a sensed temperature of the MEMS resonator,

generate a correction signal, as a function of the sensed temperature,

apply the correction signal onboard the multi-die integrated circuit, to reduce variation in a frequency represented by the oscillation signal, relative to the temperature-dependent variation of the stiffness; and

output, to a device external to the multi-die integrated circuit:

the oscillation signal; and

at least one signal that conveys to the device the sensed temperature and information representing frequency behavior of the oscillation signal as a function of the sensed temperature, for compensation, external to the multi-die integrated circuit, of additional frequency error in the oscillation signal.

2 . The multi-die integrated circuit of claim 1 wherein the circuitry is operable to generate a bias voltage to be applied to the MEMS resonator, and to apply the correction signal to vary the bias voltage in dependence on the sensed temperature, to thereby reduce the variation in the frequency of the oscillation signal relative to the temperature-dependent variation of the stiffness.

3 . The multi-die integrated circuit of claim 1 wherein:

the at least one signal coneys one or more digital correction factors which are adapted for application by an electronic circuit, external to the multi-die integrated circuit;

the circuits' die comprises a temperature sensor; and

the temperature sensor is operable to generate the second signal.

4 . The multi-die integrated circuit of claim 3 wherein the temperature sensor comprises a thermistor.

5 . The multi-die integrated circuit of claim 3 wherein the first die comprises a first resonator and a second resonator, the first resonator and the second resonator having respective resonant frequencies that diverge as a function of change in temperature, the first resonator and the second resonator and their respective resonant frequencies to serve as the temperature sensor, and wherein the circuitry is operable to look up the one or more digital correction factors from a look-up table as a function of divergence between the respective resonant frequencies.

6 . The multi-die integrated circuit of claim 1 wherein the circuits' die is in a stacked relationship with the first die, and wherein a thermally conductive material interfaces the circuits' die and the first die.

7 . The multi-die integrated circuit of claim 1 wherein the circuitry is to implement analog temperature compensation, within the circuits' die, and wherein the circuitry comprises complementary metal oxide semiconductor (CMOS) circuitry, including at least one transistor.

8 . The multi-die integrated circuit of claim 1 wherein:

the information representing frequency behavior of the oscillation signal as a function of the sensed temperature comprises polynomial coefficients; and

the polynomial coefficients are adapted for use by a circuit-based digital compensation signal generator of the device, to correct the oscillation signal, or another timing signal based thereon, so as to reduce a high-order component of the temperature dependent variation.

9 . The multi-die integrated circuit of claim 1 wherein the circuitry comprises a locked-loop circuit, and wherein the second signal is provided to a feedback path of the locked-loop circuit so as to, onboard the multi-die integrated circuit, provide temperature-based compensation of at least a low-order component of the temperature-dependent variation.

10 . The multi-die integrated circuit of claim 1 wherein:

the circuitry is to apply the correction signal onboard the multi-die integrated circuit, to reduce variation in a frequency represented by the oscillation signal, relative to the temperature-dependent variation of the stiffness, to no more than 1.0 part-per-million; and

the additional frequency error in the oscillation signal represents variation as a function of temperature which is less than 1.0 parts-per-million.

11 . The multi-die integrated circuit of claim 1 wherein circuits' die and the first die are mounted in a flip-chip arrangement.

12 . The multi-die integrated circuit of claim 1 wherein the circuitry comprises sense-sustain circuitry for the MEMS resonator and a variable capacitance or variable delay element, and wherein the second signal is provided to the variable capacitance or variable delay element, onboard the multi-die integrated circuit, so as to adjust a drive signal generated for the MEMS resonator by the sense-sustain circuitry and thereby provide temperature-based compensation of at least a low-order component of the temperature-dependent variation.

13 . The multi-die integrated circuit of claim 1 wherein the circuitry comprises a Pierce oscillator.

14 . A multi-die integrated circuit comprising:

a die stack, including a first die and a circuits' die, stacked together in a flip-chip arrangement;

the first die having thereon a microelectromechanical systems (MEMS) resonator, wherein the MEMS resonator has a stiffness that is characterized by a temperature-dependent variation;

the circuits' die having circuitry to receive a first signal, the first signal representing a frequency of vibration of the MEMS resonator, and to generate therefrom an oscillation signal for output by the multi-die integrated circuit;

wherein the circuitry is further operable to:

receive a second signal representing a sensed temperature of the MEMS resonator,

generate a correction signal, as a function of the sensed temperature,

apply the correction signal onboard the multi-die integrated circuit, to reduce variation in a frequency represented by the oscillation signal, relative to the temperature-dependent variation of the stiffness; and

output, to a device external to the multi-die integrated circuit:

the oscillation signal; and

at least one signal that conveys to the device the sensed temperature and information representing frequency behavior of the oscillation signal as a function of the sensed temperature, for compensation, external to the multi-die integrated circuit, of the additional frequency error in the oscillation signal.

15 . An apparatus comprising:

a multi-die oscillator integrated circuit, having:

a first die having thereon a microelectromechanical systems (MEMS) resonator, wherein the MEMS resonator has a stiffness that is characterized by a temperature-dependent variation; and

a circuits' die having first circuitry to receive a first signal, the first signal representing a frequency of vibration of the MEMS resonator, and to generate therefrom an oscillation signal for output by the multi-die integrated circuit; and

a device external to the multi-die oscillator integrated circuit, the device having second circuitry;

wherein the first circuitry is further operable to:

receive a second signal representing a sensed temperature of the MEMS resonator,

generate a correction signal, as a function of the sensed temperature,

apply the correction signal onboard the multi-die integrated circuit, to reduce variation in a frequency represented by the oscillation signal, relative to the temperature-dependent variation of the stiffness;

output, to the device external to the multi-die integrated circuit:

the oscillation signal; and

at least one signal that conveys to the device the sensed temperature and information representing frequency behavior of the oscillation signal as a function of the sensed temperature;

wherein the second circuitry is operable to electronically compensate for additional frequency error in the oscillation signal by generating a timing signal from the oscillation signal, the timing signal having reduced temperature-dependent variation in frequency relative to the oscillation signal.

16 . The apparatus of claim 15 wherein the first circuitry is operable to generate a bias voltage to be applied to the MEMS resonator, and to apply the correction signal to vary the bias voltage in dependence on the sensed temperature, to thereby reduce the variation in the frequency of the oscillation signal relative to the temperature-dependent variation of the stiffness.

17 . The apparatus of claim 15 wherein:

the at least one signal coneys one or more digital correction factors which are adapted for application by the second circuitry to reduce the additional frequency error;

the circuits' die comprises a temperature sensor; and

the temperature sensor is operable to generate the second signal.

18 . The apparatus of claim 17 wherein the temperature sensor comprises a thermistor.

19 . The apparatus of claim 17 wherein the first die comprises a first resonator and a second resonator, the first resonator and the second resonator having respective resonant frequencies that diverge as a function of change in temperature, the first resonator and the second resonator and their respective resonant frequencies to serve as the temperature sensor, and wherein the first circuitry is operable to look up the one or more digital correction factors from a look-up table as a function of divergence between the respective resonant frequencies.

20 . The apparatus of claim 15 wherein the circuits' die is in a stacked relationship with the first die, and wherein a thermally conductive material interfaces the circuits' die and the first die.

21 . The multi-die integrated circuit of claim 15 wherein the first circuitry is to implement analog temperature compensation, within the circuits' die, and wherein the first circuitry comprises complementary metal oxide semiconductor (CMOS) circuitry, including at least one transistor.

22 . The apparatus of claim 15 wherein:

the information representing frequency behavior of the oscillation signal as a function of the sensed temperature comprises polynomial coefficients; and

the polynomial coefficients are adapted for use by a circuit-based digital compensation signal generator of the device, to correct the oscillation signal, or another timing signal based thereon, so as to reduce a high-order component of the temperature dependent variation.

23 . The apparatus of claim 15 wherein the first circuitry comprises a locked-loop circuit, and wherein the second signal is provided to a feedback path of the locked-loop circuit so as to, onboard the multi-die integrated circuit, provide temperature-based compensation of at least a low-order component of the temperature-dependent variation.

24 . The apparatus of claim 15 wherein:

the first circuitry is to apply the correction signal onboard the multi-die integrated circuit, to reduce variation in a frequency represented by the oscillation signal, relative to the temperature-dependent variation of the stiffness, to no more than 1.0 part-per-million; and

the additional frequency error in the oscillation signal represents variation as a function of temperature which is less than 1.0 parts-per-million.

25 . The apparatus of claim 15 wherein circuits' die and the first die are mounted in a flip-chip arrangement.

26 . The apparatus of claim 15 wherein the first circuitry comprises sense-sustain circuitry for the MEMS resonator and a variable capacitance or variable delay element, and wherein the second signal is provided to the variable capacitance or variable delay element, onboard the multi-die integrated circuit, so as to adjust a drive signal generated for the MEMS resonator by the sense-sustain circuitry and thereby provide temperature-based compensation of at least a low-order component of the temperature-dependent variation.

Assignments (2)
SECURITY INTEREST Recorded Jun 30, 2026
From: SITIME CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 075862/0712 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2025
From: TABATABAEI, SASSAH; SÖNMEZ, UGUR; SOURI, KAMRAN; HEIDARY SHALMANY, SALEH
To: SITIME CORPORATION
Reel/Frame 070758/0281 →
Continuity (8)
Continuation 18745082 · Jun 17, 2024
Continuation 18464635 · Sep 11, 2023
Continuation 17973851 · Oct 26, 2022
Continuation 17544171 · Dec 7, 2021
Division 17199314 · Mar 11, 2021
Division 16782634 · Feb 5, 2020
Division 16004283 · Jun 8, 2018
Provisional Application 62517396 · Jun 9, 2017
References Cited (13)
US 5451892A · Bailey · 1995 [cited by applicant]
US 6420938B1 · Hoff · 2002 [cited by applicant]
US 7212076B1 · Taheri · 2007 [cited by examiner]
US 10594301B1 · Heidary Shalmany · 2020 [cited by applicant]
US 10979031B1 · Heidary Shalmany · 2021 [cited by applicant]
US 11228302B1 · Heidary Shalmany · 2022 [cited by applicant]
US 11528014B1 · Heidary Shalmany · 2022 [cited by applicant]
US 12047071B1 · Heidary Shalmany · 2024 [cited by applicant]
US 20030067361A1 · Takahashi · 2003 [cited by examiner]
US 20050012561A1 · Young · 2005 [cited by examiner]
US 20060261703A1 · Quevy · 2006 [cited by applicant]
US 20140091868A1 · Ishikawa · 2014 [cited by examiner]
US 20140361844A1 · Quevy · 2014 [cited by examiner]