PRESERVING ACCESS TO EDGE COUPLING COMPONENTS ON A WAFER PACKAGE
The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve techniques for packaging an electro-photonic circuit while preserving access to a grating coupler, which may involve using a sacrificial die and/or a sacrificial cap in conjunction with a unique overmolding process. Additional examples involve techniques for preserving access to an edge coupling structure.
1 . A method for packaging an electro-photonic circuit, comprising:
obtaining a wafer having an optical region formed in a side surface of the wafer, the optical region being designed to allow one or more fibers to be coupled to waveguides that are formed within the wafer and accessible via one or more structures formed in the side surface of the wafer;
positioning a sacrificial cap over a top surface of the wafer covering the optical region, wherein the sacrificial cap includes a recess formed therein, and wherein the recess is positioned over a portion of the optical region when the sacrificial cap is placed over the top surface of the wafer;
depositing an overmold over the wafer and over the sacrificial cap; and
grinding down a top surface of the overmold, wherein grinding down the top surface of the overmold includes grinding down from a top portion of the sacrificial cap to expose an opening at a top of the recess positioned over the portion of the optical region.
2 . The method of claim 1 , further comprising coupling the one or more fibers to the waveguides formed within the wafer via the one or more structures formed in the side surface of the wafer.
3 . The method of claim 2 , wherein the one or more structures are v-grooves formed within the side surface of the wafer.
4 . The method of claim 1 , wherein the waveguides couple components of the electro-photonic circuit with one or more additional components off-chip from the electro-photonic circuit.
5 . The method of claim 1 , further comprising, prior to depositing the overmold over the top surface of the wafer, disposing one or more electronic components on the top surface of the wafer, wherein disposing the one or more electronic components over the top surface of the wafer comprises connecting electrical contacts on the one or more electronic components to bumps on the top surface of the wafer and forming electro-optical paths to and from the one or more electronic components to the optical region via waveguides formed within the wafer.
6 . The method of claim 5 , wherein the one or more electronic components include one or more of a processor component, a memory component, or an analog mixed signal (AMS) block.
7 . The method of claim 1 , wherein, prior to grinding down the top surface of the overmold, the top portion of the sacrificial cap extends over a top of the recess, and wherein the top portion of the sacrificial cap has a thickness of greater than 25 microns.
8 . The method of claim 1 , wherein a thickness between a top and bottom surface of the sacrificial cap prior to grinding down the top surface of the overmold is less than 1000 microns.
9 . The method of claim 1 , wherein the overmold does not flow between the sacrificial cap and the wafer.
10 . The method of claim 1 , wherein the sacrificial cap is made from a same material as a material of the overmold that is deposited over the wafer.
11 . The method of claim 1 , wherein the sacrificial cap is made from a different material as a material of the overmold that is deposited over the wafer.
12 . The method of claim 1 , wherein the wafer comprises a first package portion and a second package portion adjacent to the first package portion, the first package portion having one or more electronic components deposited thereon, the optical region being formed in a region between the first package portion and the second package portion.
13 . The method of claim 12 , further comprising dicing vertically between a top surface and a bottom surface of the wafer and through a portion of the recess, wherein dicing vertically between the top surface and the bottom surface of the wafer through the portion of the recess provides lateral access to the side surface of the wafer having the one or more structures formed therein.
14 . The method of claim 13 , further comprising coupling the one or more fibers to the waveguides via the laterally accessible side surface, wherein coupling the one or more fibers to the waveguides causes the one or more fibers to be optically coupled to the one or more electronic components via the waveguides formed within the wafer.
15 . The method of claim 1 , wherein the side surface is formed within one of:
an interior side surface formed within an outer perimeter of the wafer; or
an exterior side surface formed around the outer perimeter of the wafer.
16 . A method for packaging an electro-photonic circuit, comprising:
obtaining a photonic integrated circuit (PIC) wafer comprising:
an optical region formed in a side surface of the PIC wafer, the optical region being designed to allow one or more fibers to be coupled to waveguides that are formed within the PIC wafer and accessible via one or more structures formed in the side surface of the PIC wafer; and
optical transmitter and receiver portions in optical communication with the optical region, the optical transmitter and receiver portions having electrical interconnects to a top surface of the PIC wafer in a portion that does not extend into the optical region;
disposing one or more electronic components on the PIC wafer, the one or more electronic components including electrical transmitter and receiver portions interconnected with the optical transmitter and receiver portions and forming electro-optical paths to and from the one or more electronic components to the optical region;
positioning a sacrificial cap over a top surface of the PIC wafer covering the optical region, wherein the sacrificial cap includes a recess formed therein, and wherein the recess is positioned over a portion of the optical region when the sacrificial cap is placed over the top surface of the PIC wafer;
depositing an overmold over the PIC wafer, the one or more electronic components, and the sacrificial cap; and
grinding down a top surface of the overmold, wherein grinding down the top surface of the overmold includes grinding down from a top portion of the sacrificial cap to create an opening at a top of the recess positioned over the portion of the optical region.
17 . The method of claim 16 , further comprising coupling the one or more fibers to the waveguides formed within the PIC wafer via the one or more structures on the side surface of the PIC wafer.
18 . The method of claim 17 , wherein the one or more side structures are one or more v-grooves formed within the side surface of the PIC wafer.
19 . The method of claim 16 , wherein the waveguides couple components of the electro-photonic circuit with one or more additional components off-chip from the electro-photonic circuit.
20 . The method of claim 16 , further comprising, prior to depositing the overmold over the top surface of the PIC wafer, disposing one or more electronic components on the top surface of the PIC wafer, wherein disposing the one or more electronic components over the top surface of the PIC wafer comprises connecting electrical contacts on the one or more electronic components to bumps on the top surface of the PIC wafer and forming electro-optical paths to and from the one or more electronic components to the optical region via waveguides formed within the PIC wafer.
21 . The method of claim 20 , wherein the one or more electronic components include one or more of a processor component, a memory component, or an analog mixed signal (AMS) block.
22 . The method of claim 16 , wherein, prior to grinding down the top surface of the overmold, the top portion of the sacrificial cap extends over a top of the recess, and wherein the top portion of the sacrificial cap has a thickness of greater than 25 microns.
23 . The method of claim 16 , wherein a thickness between a top and bottom surface of the sacrificial cap prior to grinding down the top surface of the overmold is less than 1000 microns.
24 . The method of claim 16 , wherein the overmold does not flow between the sacrificial cap and the PIC wafer.
25 . The method of claim 16 , wherein the sacrificial cap is made from a same material as a material of the overmold that is deposited over the PIC wafer.
26 . The method of claim 16 , wherein the sacrificial cap is made from a different material as a material of the overmold that is deposited over the PIC wafer.
27 . The method of claim 16 , wherein the PIC wafer comprises a first package portion and a second package portion adjacent to the first package portion, the first package portion having the one or more electronic components deposited thereon, the optical region being formed in a region between the first package portion and the second package portion.
28 . The method of claim 27 , further comprising dicing vertically between a top surface and a bottom surface of the PIC wafer and through a portion of the recess, wherein dicing vertically between the top surface and the bottom surface of the PIC wafer through the portion of the recess provides lateral access to the side surface of the PIC wafer having the one or more structures formed therein.
29 . The method of claim 28 , further comprising coupling the one or more fibers to the waveguides via the laterally accessible side surface, wherein coupling the one or more fibers to the waveguides causes the one or more fibers to be optically coupled to the one or more electronic components via the waveguides formed within the PIC wafer.
30 . The method of claim 16 , wherein the side surface is formed within one of:
an interior side surface formed within an outer perimeter of the PIC wafer; or
an exterior side surface formed around the outer perimeter of the PIC wafer.