IP Library › Patent Application 19181010
Patent Application
App. No. 19/181,010

TECHNIQUES FOR MANAGING MEMORY EXCEPTION HANDLING

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Quick Facts
Patent No.
US None
App. No.
19/181,010
Abstract

Methods, systems, and devices for techniques for managing memory exception handling are described. A memory device may write first data associated with a first access command to a first portion of a buffer of a memory device. The memory device may determine a programming failure to write second data to a page of a first block of the memory device. In response to determining the programming failure, the memory device may perform an access operation associated with the first access command to vacate the first data from the first portion of the buffer. In response, the memory device may write the second data to the first portion of the buffer. The memory device may write the second data from the first portion of the buffer to a page of a second block of the memory device in response to writing the second data to the first portion of the buffer.

Claims (54)

1 . (canceled)

2 . A memory system, comprising:

one or more memory devices; and

one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:

perform an access operation to vacate first data from a first portion of a buffer of the one or more memory devices in response to a failure to program second data to a first page of a first block of the one or more memory devices, wherein the first portion of the buffer is allocated for the first data;

write the second data to the first portion of the buffer in response to performing the access operation; and

write the second data from the first portion of the buffer to a first page of a second block of the one or more memory devices.

3 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:

write the second data to a register of the one or more memory devices in response to the failure; and

write the second data from the register to the first portion of the buffer.

4 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:

write third data from a second page of the first block that precedes the first page of the first block to a second page of the second block as part of a maintenance operation in accordance with the failure.

5 . The memory system of claim 4 , wherein the maintenance operation is one of a wear leveling operation, garbage collection operation, relocation operation, or refresh operation.

6 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:

release the second data from the first portion of the buffer in response to writing the second data from the first portion of the buffer to the first page of the second block;

write, to the first portion of the buffer, third data from a second page preceding the first page of the first block; and

write the third data from the first portion of the buffer to a second page of the second block.

7 . The memory system of claim 6 , wherein the second page of the first block directly precedes the first page of the first block and the second page of the second block directly precedes the first page of the second block.

8 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:

refrain from performing one or more additional access operations in response to the failure.

9 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:

refrain from receiving one or more additional access commands in response to the failure.

10 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:

perform one or more additional access operations to vacate data from the buffer in response to the failure, wherein writing the second data to the first portion of the buffer is in accordance with performing the one or more additional access operations.

11 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:

allocate the first portion of the buffer to write the second data in response to performing the access operation, wherein writing the second data to the first portion of the buffer is in accordance with allocating the first portion of the buffer.

12 . A memory system, comprising:

volatile memory;

non-volatile memory; and

one or more controllers coupled with the volatile memory and the non-volatile memory and configured to cause the memory system to:

write first data to a portion of the volatile memory in response to a failure to write the first data to a first page of a first block of the non-volatile memory, wherein the portion of the volatile memory is allocated for second data;

write the first data from the portion of the volatile memory to a first page of a second block of the non-volatile memory; and

write respective data from one or more pages of the first block to one or more pages of the second block according to an ascending order or a descending order, wherein the one or more pages of the first block precede the first page of the first block.

13 . The memory system of claim 12 , wherein, to write the respective data to the second block according to the descending order, the one or more controllers are configured to cause the memory system to:

write third data from a second page of the first block to the portion of the volatile memory in response to writing the first data from the portion of the volatile memory to the first page of the second block, wherein the second page of the first block immediately precedes the first page of the first block; and

write the third data from the portion of the volatile memory to a second page of the second block, wherein the second page of the second block immediately precedes the first page of the second block.

14 . The memory system of claim 12 , wherein, to write the respective data to the second block according to the ascending order, the one or more controllers are configured to cause the memory system to:

write third data from a second page of the first block to the portion of the volatile memory in response to writing the first data from the portion of the volatile memory to the first page of the second block, wherein the second page of the first block is a beginning page of the first block; and

write the third data from the portion of the volatile memory to a second page of the second block, wherein the second page of the second block is a beginning page of the second block.

15 . The memory system of claim 12 , wherein the one or more controllers are further configured to cause the memory system to:

refrain from performing one or more additional access operations in response to the failure.

16 . The memory system of claim 12 , wherein the one or more controllers are further configured to cause the memory system to:

refrain from receiving one or more additional access commands in response to the failure.

17 . The memory system of claim 12 , wherein the portion of the volatile memory is equal to a quantity of data capable of being stored by a page of the non-volatile memory.

18 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system, cause the memory system to:

perform an access operation to vacate first data from a first portion of a buffer of the memory system in response to a failure to program second data to a first page of a first block of the memory system, wherein the first portion of the buffer is allocated for the first data;

write the second data to the first portion of the buffer in response to performing the access operation; and

write the second data from the first portion of the buffer to a first page of a second block of the memory system.

19 . The non-transitory computer-readable medium of claim 18 , wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to:

write the second data to a register of the memory system in response to the failure; and

write the second data from the register to the first portion of the buffer.

20 . The non-transitory computer-readable medium of claim 18 , wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to:

write third data from a second page of the first block that precedes the first page of the first block to a second page of the second block as part of a maintenance operation in accordance with the failure.

21 . The non-transitory computer-readable medium of claim 20 , wherein the maintenance operation is one of a wear leveling operation, garbage collection operation, relocation operation, or refresh operation.