SHORTENED SINGLE-LEVEL CELL MEMORY PROGRAMMING
A memory device comprising an array of memory cells configured as single-level cell memory. Control logic is operatively coupled to the array and is to cause a seed operation to be performed on sub-blocks of the array to precondition voltage levels of the sub-blocks for programming. The control logic causes pages of data to be programmed to respective ones of the sub-blocks. The control logic causes a program verify to be performed on memory cells of the sub-blocks after programming the pages of data. The control logic causes a check verification operation be performed at the sub-blocks to determine results of the program verify and that the pages of data have been completely programmed. The control logic exits a program operation of the sub-blocks in response to passing the check verification operation.
1 . A memory device comprising:
an array of memory cells configured as single-level cell memory; and
control logic operatively coupled to the array of memory cells, the control logic to perform operations comprising:
causing a seed operation to be performed on a plurality of sub-blocks of the array to precondition voltage levels of the plurality of sub-blocks for programming;
causing a plurality of pages of data to be programmed to respective ones of the plurality of sub-blocks;
causing a program verify to be performed on memory cells of the plurality of sub-blocks after programming the plurality of pages of data;
causing a check verification operation be performed at the plurality of sub-blocks to determine results of the program verify and that the pages of data have been completely programmed; and
exiting a program operation of the plurality of sub-blocks in response to passing the check verification operation.
2 . The memory device of claim 1 , wherein causing the program verify to be performed comprises performing a single program verify on all of the plurality of sub-blocks together after each of the plurality of sub-blocks is in a programmed state.
3 . The memory device of claim 1 , wherein the operations further comprise:
causing the plurality of pages of data to be loaded into a page buffer; and
causing hardware initialization to be performed to prepare to program the plurality of sub-blocks.
4 . The memory device of claim 1 , wherein the operations further comprise causing a scan to be performed of the plurality of sub-blocks in response to failing the check verification operation.
5 . The memory device of claim 1 , wherein causing the plurality of pages of data to be programmed comprises:
(i) causing a program pulse to be sent to a first sub-block of the plurality of sub-blocks to program a first page of the plurality of pages of data to the first sub-block;
(ii) causing a recovery operation to be performed at the first sub-block; and
(iii) causing a reduced seed operation to be performed at a second sub-block of the plurality of sub-blocks to precondition the second sub-block for programming.
6 . The memory device of claim 5 , wherein the reduced seed operation takes a period of time that is shorter than that for preconditioning the first sub-block.
7 . The memory device of claim 5 , wherein causing the plurality of pages of data to be programmed further comprises:
(iv) causing a program pulse to be sent to the second sub-block to program a second page of the plurality of pages of data to the second sub-block;
(v) causing a recovery operation to be performed at the second sub-block; and
repeating (iii) through (v) to program a remainder of the plurality of pages of data to the plurality of sub-blocks.
8 . A method comprising:
causing, by control logic of a memory device, a seed operation to be performed on a plurality of sub-blocks of an array of memory cells configured as single-level cell memory, the seed operation to precondition voltage levels of the plurality of sub-blocks for programming;
causing, by the control logic, a plurality of pages of data to be programmed to respective ones of the plurality of sub-blocks;
causing, by the control logic, a program verify to be performed on memory cells of the plurality of sub-blocks after programming the plurality of pages of data;
causing a check verification operation be performed at the plurality of sub-blocks to determine results of the program verify and that the pages of data have been completely programmed; and
exiting, by the control logic, a program operation of the plurality of sub-blocks in response to passing the check verification operation.
9 . The method of claim 8 , wherein causing the program verify to be performed comprises performing a single program verify on all of the plurality of sub-blocks together after each of the plurality of sub-blocks is in a programmed state.
10 . The method of claim 8 , further comprising:
causing the plurality of pages of data to be loaded into a page buffer; and
causing hardware initialization to be performed to prepare to program the plurality of sub-blocks.
11 . The method of claim 8 , further comprising causing a scan to be performed of the plurality of sub-blocks in response to failing the check verification operation.
12 . The method of claim 8 , wherein causing the plurality of pages of data to be programmed comprises:
(i) causing a program pulse to be sent to a first sub-block of the plurality of sub-blocks to program a first page of the plurality of pages of data to the first sub-block;
(ii) causing a recovery operation to be performed at the first sub-block; and
(iii) causing a reduced seed operation to be performed at a second sub-block of the plurality of sub-blocks to precondition the second sub-block for programming.
13 . The method of claim 12 , wherein the reduced seed operation takes a period of time that is shorter than that for preconditioning the first sub-block.
14 . The method of claim 12 , wherein causing the plurality of pages of data to be programmed further comprises:
(iv) causing a program pulse to be sent to the second sub-block to program a second page of the plurality of pages of data to the second sub-block;
(v) causing a recovery operation to be performed at the second sub-block; and
repeating (iii) through (v) to program a remainder of the plurality of pages of data to the plurality of sub-blocks.
15 . An integrated circuit comprising:
at least one die comprising an array of memory cells configured as single-level cell memory; and
control logic operatively coupled to the at least one die, the control logic to perform operations comprising:
causing a plurality of pages of data to be loaded into a page buffer that is coupled with the array of memory cells;
causing a seed operation to be performed on a plurality of sub-blocks of the array to precondition voltage levels of the plurality of sub-blocks for programming;
causing the plurality of pages of data to be programmed to respective ones of the plurality of sub-blocks;
causing a program verify to be performed on memory cells of the plurality of sub-blocks after programming the plurality of pages of data;
causing a check verification operation be performed at the plurality of sub-blocks to determine results of the program verify and that the pages of data have been completely programmed; and
causing a scan to be performed of the plurality of sub-blocks in response to failing the check verification operation.
16 . The integrated circuit of claim 15 , wherein causing the program verify to be performed comprises performing a single program verify on all of the plurality of sub-blocks together after each of the plurality of sub-blocks is in a programmed state.
17 . The integrated circuit of claim 15 , wherein the operations further comprise exiting a program operation of the plurality of sub-blocks in response to passing the check verification operation.
18 . The integrated circuit of claim 15 , wherein causing the plurality of pages of data to be programmed comprises:
(i) causing a program pulse to be sent to a first sub-block of the plurality of sub-blocks to program a first page of the plurality of pages of data to the first sub-block;
(ii) causing a recovery operation to be performed at the first sub-block; and
(iii) causing a reduced seed operation to be performed at a second sub-block of the plurality of sub-blocks to precondition the second sub-block for programming.
19 . The integrated circuit of claim 18 , wherein the reduced seed operation takes a period of time that is shorter than that for preconditioning the first sub-block.
20 . The integrated circuit of claim 18 , wherein causing the plurality of pages of data to be programmed further comprises:
(iv) causing a program pulse to be sent to the second sub-block to program a second page of the plurality of pages of data to the second sub-block;
(v) causing a recovery operation to be performed at the second sub-block; and
repeating (iii) through (v) to program a remainder of the plurality of pages of data to the plurality of sub-blocks.