AMORPHOUS METAL THIN FILM TRANSISTORS
Described herein are various amorphous metal thin film transistors. Embodiments of such transistors include an amorphous metal gate electrode and a channel conductor formed on a non-conducting substrate. Further embodiments of such transistors include an amorphous metal source electrode, an amorphous metal drain electrode, and a channel conductor formed on a non-conducting substrate. Methods of forming such transistors are also described.
1 . A method, comprising:
forming a first insulating layer on a support substrate;
forming a channel conductor on the first insulating layer;
forming a source electrode and a drain electrode each overlapping a portion of the channel conductor, wherein each of the source and drain electrodes comprise an amorphous metal alloy;
forming a second insulating layer on the source and drain electrodes; and
forming a gate electrode on the second insulating layer, wherein the gate electrode overlaps a portion of the source electrode and a portion of the drain electrode.
2 . The method of claim 1 , wherein the gate electrode comprises an amorphous metal alloy.
3 - 13 . (canceled)
14 . The method of claim 1 , wherein the channel conductor is formed of a semiconductor material.
15 . The method of claim 1 , wherein the second insulating layer comprises a metal oxide or a metal nitride.
16 . The method of claim 1 , wherein the second insulating layer less than or equal to 10 nm in thickness.
17 . The method of claim 16 , wherein the second insulating layer is deposited by atomic layer deposition.
18 . The method of claim 16 , wherein the second insulating layer comprises aluminum oxide.
19 . The method of claim 1 , wherein the gate electrode is substantially aligned with the channel conductor.
20 . The method of claim 1 , wherein the source drain electrodes each overlap an opposite portion of the channel conductor.
21 . A method, comprising:
forming first insulating layer on a support substrate;
forming a channel conductor on the first insulating layer;
forming a source electrode and a drain electrode on a first portion of the insulating layer, wherein the source electrode and the drain electrode each overlap a portion of the channel conductor, and wherein each of the source and drain electrodes comprise an amorphous metal alloy;
forming metal interconnect on a second portion of the first insulator;
forming a second insulating layer on the source and drain electrodes and the metal interconnect;
forming a gate electrode on a first portion of the second insulating layer, wherein the gate electrode overlaps a portion of the source electrode and a portion of the drain electrode;
forming a first electrode and a second electrode on a second portion of the second insulating layer, wherein the first and second electrodes each overlap a portion of the metal interconnect.
22 . The method of claim 21 , wherein the metal interconnect comprises an amorphous metal alloy.
23 . The method of claim 21 , wherein the gate electrode, the first electrode, and the second electrode comprises an amorphous metal alloy.
24 . An amorphous metal thin film transistor (AMTFT), comprising:
a support substrate
a first insulating layer on the support substrate;
a channel conductor on the first insulating layer;
a source electrode and a drain electrode, wherein the source electrode and the drain electrode each overlap a portion of the channel conductor, and wherein each of the source and drain electrodes comprise an amorphous metal alloy;
a second insulating layer on the source and drain electrodes; and
a gate electrode on the second insulating layer, wherein the gate electrode overlaps a portion of the source electrode and a portion of the drain electrode.
25 . The AMTFT of claim 24 , wherein the gate electrode comprises an amorphous metal alloy.
26 . The AMTFT of claim 24 , wherein the second insulating layer comprises a metal oxide or a metal nitride.
27 . The AMTFT of claim 24 , wherein the thickness of the second insulating layer is less than or equal to 10 nm.
28 . A display, comprising the AMTFT of claim 24 .
29 . The display of claim 28 , comprising a pixel, wherein the pixel is controlled by the AMTFT.
30 . A device, comprising the AMTFT of claim 24 and an amorphous metal non-linear resistor (AMNR), wherein the AMTFT and the AMNR are formed on a single substrate.
31 . A display, comprising the device of claim 30 and a pixel, wherein the pixel is controlled by the device.