EFFICIENT MEMORY USE TO SUPPORT SOFT INFORMATION IN BIT FLIPPING DECODERS
A method includes performing a read operation of a first codeword including first hard data and generating an error vector using a reliability metric of the first hard data. The first hard data and error vector are stored in first and second portions of memory. A first corrected codeword is returned that combines the error vector and the hard data from the first and second portions of memory. A read operation of a second codeword is performed, including second hard data and soft information. The hard data and soft information are stored in the first and second portions of memory. A bit of second hard data is flipped responsive to comparing a reliability metric of the bit of the second hard data to a bit flipping threshold, wherein flipping the bit includes updating the second hard data. The updated second codeword is returned resulting from reading the portions of memory.
1 . A method comprising:
determining whether to enable soft information mode in a read operation a codeword for a bit flipping decoder;
performing the read operation of the codeword including hard data, wherein the read operation includes soft information when the soft information mode is enabled and the read operation excludes soft information when the soft information is not enabled;
storing the hard data in a first portion of memory; and
decoding the codeword in multiple iterations of the bit flipping decoder, wherein at least one of the multiple iterations includes a determination to flip a bit of the hard data and, in response to the determination to flip the bit:
flipping a bit of an error vector in a second portion of memory corresponding to the bit of hard data when the soft information is not enabled, maintaining the bit of hard data in a static state in the first portion of memory during the multiple iterations, and
flipping the bit of hard data stored in the first portion of memory when the soft information mode is enabled.
2 . The method of claim 1 , further comprising:
initializing the error vector to include a value of zero corresponding to each bit of the codeword when the soft information is not enabled.
3 . The method of claim 2 , further comprising:
outputting corrected values of the codeword by combining the error vector from the second portion of memory with the static hard data from the first portion of memory.
4 . The method of claim 1 , wherein the soft information is stored in the second portion of the memory when the soft information mode is enabled.
5 . The method of claim 1 , further comprising:
selecting a bit flipping threshold using the soft information of the bit of the hard data when the soft information mode is enabled.
6 . The method of claim 1 , wherein determining whether to enable soft information mode includes determining the read operation is directed to a low-reliability portion of memory.
7 . The method of claim 6 , wherein determining the read operation is directed to a low-reliability portion of memory includes looking up an address for the read operation directed in a data structure associated with weak wordlines.
8 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
determine whether to enable soft information mode in a read operation a codeword for a bit flipping decoder;
perform the read operation of the codeword including hard data, wherein the read operation includes soft information when the soft information mode is enabled and the read operation excludes soft information when the soft information is not enabled;
store the hard data in a first portion of memory; and
decode the codeword in multiple iterations of the bit flipping decoder, wherein at least one of the multiple iterations includes a determination to flip a bit of the hard data and, in response to the determination to flip the bit:
flip a bit of an error vector in a second portion of memory corresponding to the bit of hard data when the soft information is not enabled, maintaining the bit of hard data in a static state in the first portion of memory during the multiple iterations, and
flip the bit of hard data stored in the first portion of memory when the soft information mode is enabled.
9 . The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:
initialize the error vector to include a value of zero corresponding to each bit of the codeword when the soft information is not enabled.
10 . The non-transitory computer-readable storage medium of claim 9 , wherein the processing device is further to:
output corrected values of the codeword by combining the error vector from the second portion of memory with the static hard data from the first portion of memory.
11 . The non-transitory computer-readable storage medium of claim 8 , wherein the soft information is stored in the second portion of the memory when the soft information mode is enabled.
12 . The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:
select a bit flipping threshold using the soft information of the bit of the hard data when the soft information mode is enabled.
13 . The non-transitory computer-readable storage medium of claim 8 , wherein determining whether to enable soft information mode includes determining the read operation is directed to a low-reliability portion of memory.
14 . The non-transitory computer-readable storage medium of claim 13 , wherein determining the read operation is directed to a low-reliability portion of memory includes looking up an address for the read operation directed in a data structure associated with weak wordlines.
15 . A system comprising:
a memory device and
a processing device, operatively coupled with the memory device, to:
determine whether to enable soft information mode in a read operation a codeword for a bit flipping decoder, wherein determining whether to enable soft information mode includes determining the read operation is directed to a low-reliability portion of memory;
perform the read operation of the codeword including hard data, wherein the read operation includes soft information when the soft information mode is enabled and the read operation excludes soft information when the soft information is not enabled;
store the hard data in a first portion of memory; and
decode the codeword in multiple iterations of the bit flipping decoder, wherein at least one of the multiple iterations includes a determination to flip a bit of the hard data and, in response to the determination to flip the bit:
flip a bit of an error vector in a second portion of memory corresponding to the bit of hard data when the soft information is not enabled, maintaining the bit of hard data in a static state in the first portion of memory during the multiple iterations, and
flip the bit of hard data stored in the first portion of memory when the soft information mode is enabled.
16 . The system of claim 15 , wherein the processing device is further to:
initialize the error vector to include a value of zero corresponding to each bit of the codeword when the soft information is not enabled.
17 . The system of claim 16 , wherein the processing device is further to:
output corrected values of the codeword by combining the error vector from the second portion of memory with the static hard data from the first portion of memory.
18 . The system of claim 15 , wherein the soft information is stored in the second portion of the memory when the soft information mode is enabled.
19 . The system of claim 15 , wherein the processing device is further to:
select a bit flipping threshold using the soft information of the bit of the hard data when the soft information mode is enabled.
20 . The system of claim 15 , wherein determining the read operation is directed to a low-reliability portion of memory includes looking up an address for the read operation directed in a data structure associated with weak wordlines.