SOFT READ OPERATIONS WITH PROGRESSIVE DATA OUTPUT

1 - 20 . (canceled)

21 . A memory device comprising:

a plurality of memory cells; and

logic circuitry to:

receive, from a controller, an initial request;

based at least in part on receiving the initial request, conduct a soft-read from at least one memory cell of the plurality of memory cells;

generate, via the soft-read, first soft-bit information and second soft-bit information;

transmit the first soft-bit information to the controller while withholding at least the second soft-bit information from the controller;

detect a subsequent request from the controller; and

based at least in part on detecting the subsequent request, send the second soft-bit information to the controller.

22 . The memory device of claim 21 , wherein the logic circuitry is further to:

based at least in part on receiving the initial request, conduct a hard-read from the at least one memory cell;

generate, via the hard-read, hard-bit information; and

transmit the hard-bit information with the first soft-bit information to the controller.

23 . The memory device of claim 22 , wherein the logic circuitry is further to store at least the second soft-bit information locally on the memory device while the hard-bit information is being processed by the controller.

24 . The memory device of claim 22 , wherein the logic circuitry is to transmit the hard-bit information to the controller via a shared bus.

25 . The memory device of claim 21 , wherein the logic circuitry is further to:

maintain a voltage of a wordline associated with the at least one memory cell at a read voltage level; and

compare a current of a bitline associated with the at least one memory cell to a plurality of reference current levels.

26 . The memory device of claim 21 , wherein the soft-read comprises one or more of a 5-strobe soft-read or a 7-strobe soft-read.

27 . The memory device of claim 21 , wherein the logic circuitry is disposed at one or more substrates.

28 . A memory chip controller comprising:

logic circuitry, wherein the logic circuitry is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, and wherein the logic circuitry is to:

trigger, via an initial request, a soft-read with respect to at least one memory cell at a memory device;

generate, via the soft-read, first soft-bit information and second soft-bit information;

conduct an error correction on the first soft-bit information; and

issue a subsequent request for at least the second soft-bit information if the error correction is unsuccessful.

29 . The memory chip controller of claim 28 , wherein the logic circuitry is further to:

trigger, via the initial request, a hard-read with respect to the at least one memory cell;

generate hard-bit information; and

conduct the error correction on the hard-bit information.

30 . The memory chip controller of claim 29 , wherein the logic circuitry is to store the hard-bit information locally on the memory chip controller until the second soft-bit information is received from the memory device.

31 . The memory chip controller of claim 28 , wherein the error correction is a first error correction, and wherein the logic circuitry is further to conduct a second error correction on the second soft-bit information.

32 . The memory chip controller of claim 31 , wherein the logic circuitry is further to obtain the first soft-bit information and the second soft-bit information from a shared bus.

33 . The memory chip controller of claim 28 , wherein the logic circuitry is further to exclude the second soft-bit information from the error correction.

34 . The memory chip controller of claim 28 , wherein the soft-read comprises one or more of a 5-strobe soft-read or a 7-strobe soft-read.

35 . A system comprising:

a memory chip controller comprising first logic circuitry, wherein the first logic circuitry is to:

trigger, via an initial request, a soft-read at a memory device;

generate, via the soft-read, first soft-bit information and second soft-bit information;

receive the first soft-bit information;

conduct an error correction on the first soft-bit information; and

issue a subsequent request for at least the second soft-bit information if the error correction is unsuccessful; and

the memory device comprising a plurality of memory cells and second logic circuitry, wherein the second logic circuitry is to:

receive the initial request;

based at least in part on receiving the initial request, conduct the soft-read from at least one memory cell of the plurality of memory cells;

transmit the first soft-bit information to the memory chip controller; and

withhold at least the second soft-bit information from the memory chip controller until the subsequent request is received.

36 . The system of claim 35 , wherein:

the first logic circuitry is further to:

trigger, via the initial request, a hard-read to generate hard-bit information; and

conduct the error correction on the hard-bit information; and

the second logic circuitry is further to:

based at least in part on receiving the initial request, conduct the hard-read from the at least one memory cell;

generate, via the hard-read, the hard-bit information;

transmit the hard-bit information with the first soft-bit information to the memory chip controller.

37 . The system of claim 35 , wherein the error correction is a first error correction, and wherein the first logic circuitry is to conduct a second error correction on the second soft-bit information.

38 . The system of claim 35 , wherein the first logic circuitry is to obtain the first soft-bit information and the second soft-bit information from a shared bus.

39 . The system of claim 35 , wherein the second logic circuitry is further to:

maintain a voltage of a wordline associated with the at least one memory cell at a read voltage level, and

compare a current of a bitline associated with the at least one memory cell to a plurality of reference current levels.

40 . The system of claim 35 , wherein the soft-read comprises one or more of a 5-strobe soft-read or a 7-strobe soft-read.