HOST VERIFICATION FOR A MEMORY DEVICE
Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.
1 . A memory system, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
receive, at a memory device of the one or more memory devices, an identifier of a host device after a transition from a first power mode of the memory device to a first functionality mode of a second power mode of the memory device, the second power mode comprising the first functionality mode and a second functionality mode;
transmit a first value that is generated based at least in part on the identifier of the host device, the first value comprising a random set of bits;
receive, in response to transmitting the first value, a signal that comprises a third value; and
refrain from validating the host device based at least in part on determining that the third value is different from a fourth value that is generated based at least in part on the first value and a secret stored at the memory device.
2 . The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
increment a counter associated with the third value to a first count value based at least in part on determining that the third value is different from the fourth value; and
determine that the first count value satisfies a threshold value based at least in part on comparing the third value with the fourth value.
3 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
disable the second functionality mode of the memory device based at least in part on determining that the first count value satisfies the threshold value.
4 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
transmit an alert based at least in part on determining that the first count value satisfies the threshold value.
5 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
adjust the threshold value based at least in part on one or more events at the memory device.
6 . The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
generate the fourth value using a randomization process on the first value before receiving the third value.
7 . The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
disable the second functionality mode of the memory device before a process associated with the transition is completed.
8 . A memory system, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
transition a memory device of the one or more memory devices from a first power mode to a first functionality mode of a second power mode, the second power mode comprising the first functionality mode and a second functionality mode;
receive an access command and a first value associated with an identification of the access command; and
refrain from executing the access command based at least in part on determining that the first value is different from a second value generated based at least in part on the first value and a secret stored at the memory device.
9 . The memory system of claim 8 , wherein the one or more controllers are further configured to cause the memory system to:
increment a counter associated with the first value to a first count value based at least in part on determining that the first value is different from the second value; and
determine that the first count value satisfies a threshold quantity of invalid access commands based at least in part on comparing the first value with the second value.
10 . The memory system of claim 9 , wherein the one or more controllers are further configured to cause the memory system to:
disable the second functionality mode of the memory device based at least in part on determining that the first count value satisfies the threshold quantity.
11 . The memory system of claim 9 , wherein the one or more controllers are further configured to cause the memory system to:
transmit an alert based at least in part on determining that the first count value satisfies the threshold quantity.
12 . The memory system of claim 9 , wherein the one or more controllers are further configured to cause the memory system to:
adjust the threshold quantity based at least in part on one or more events at the memory device.
13 . The memory system of claim 8 , wherein the access command and the first value are received concurrently.
14 . A method, comprising:
receiving, at a memory device of one or more memory devices, an identifier of a host device after a transition from a first power mode of the memory device to a first functionality mode of a second power mode of the memory device, the second power mode comprising the first functionality mode and a second functionality mode;
transmitting a first value that is generated based at least in part on the identifier of the host device, the first value comprising a random set of bits;
receiving, in response to transmitting the first value, a signal that comprises a third value; and
refraining from validating the host device based at least in part on determining that the third value is different from a fourth value that is generated based at least in part on the first value and a secret stored at the memory device.
15 . The method of claim 14 , further comprising:
receiving, in the signal, an access command and the third value, wherein the third value is associated with an identification of the access command; and
refraining from executing the access command based at least in part on refraining from validating the host device.
16 . The method of claim 14 , further comprising:
incrementing a counter associated with the first value to a first count value based at least in part on determining that the third value is different from the fourth value; and
determining that the first count value satisfies a threshold value based at least in part on comparing the third value with the fourth value.
17 . The method of claim 16 , further comprising:
disabling the second functionality mode of the memory device based at least in part on determining that the first count value satisfies the threshold value.
18 . The method of claim 16 , further comprising:
transmitting an alert based at least in part on determining that the first count value satisfies the threshold value.
19 . The method of claim 16 , further comprising:
adjusting the threshold value based at least in part on one or more events at the memory device.
20 . The method of claim 14 , further comprising:
disabling the second functionality mode of the memory device before a process associated with the transition is completed.