METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A COHERENT VICTIM CACHE WITH PARALLEL DATA PATHS
Methods, apparatus, systems and articles of manufacture are disclosed facilitate read-modify-write support in a coherent victim cache with parallel data paths. An example apparatus includes a random-access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random-access memory configured to obtain a read request indicating a first address to read via a snoop interface, an address encoder coupled to the random-access memory, the address encoder to, when the random-access memory indicates a hit of the read request, generate a second address corresponding to a victim cache based on the first address, and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.
1 . A method, comprising:
obtaining, by a first cache level, a snoop request from a second cache level, wherein the first cache level includes a first cache memory and a second cache memory storing data evicted from the first cache memory;
generating, based on the snoop request, a read operation directed to an address;
determining whether the read operation corresponds to a hit in the second cache memory; and
based on determining that the read operation corresponds to a hit in the second cache memory,
determining whether there is a pending write operation directed to the address;
based on determining that there is a pending write operation directed to the address,
obtaining data of the pending write operation; and
providing the data to the second cache level.
2 . The method of claim 1 , wherein:
the first cache level is a level-one (L1) cache; and
the second cache level is a level-two (L2) cache.
3 . The method of claim 1 , wherein:
the first cache memory is a main storage; and
the second cache memory is a victim storage.
4 . The method of claim 1 , wherein the data of the pending write operation is stored in a store queue coupled to the second cache memory.
5 . The method of claim 1 , wherein:
the first cache level comprises a tag random access memory; and
determining whether the read operation corresponds to a hit in the second cache memory comprises determining whether the read operation corresponds to a hit in the second cache memory based on content of the tag random access memory.
6 . The method of claim 1 , comprising:
based on determining that there is no pending write operation directed to the address, obtaining data from the second cache memory; and
providing the data to the second cache level.
7 . The method of claim 1 , comprising:
based on determining that the read operation corresponds to a hit in the second cache memory,
determining a modified, exclusive, shared, or invalid (MESI) state associated with the address of the second cache memory.
8 . The method of claim 7 , wherein:
the first cache level comprises a random access memory; and
determining the MESI state comprises determining the MESI state based on content of the random access memory.
9 . The method of claim 1 , comprising:
based on determining that the read operation corresponds to a hit in the second cache memory, translating the address into an address space of the second cache memory.
10 . The method of claim 1 , wherein:
the first cache level comprises a first interface and a second interface; and
the first interface has a width different from the second interface.
11 . A system, comprising:
a first cache level that includes:
a first cache memory;
a second cache memory capable of storing data evicted from the first cache memory; and
a cache controller capable of:
obtaining a snoop request from a second cache level;
generating, based on the snoop request, a read operation directed to an address indicated by the snoop request;
determining whether the read operation corresponds to a hit in the second cache memory; and
based on determining that the read operation corresponds to a hit in the second cache memory,
determining whether there is a pending write operation directed to the address;
based on determining that there is a pending write operation directed to the address,
obtaining data of the pending write operation; and
providing the data to the second cache level.
12 . The system of claim 11 , wherein:
the first cache level is a level-one (L1) cache; and
the second cache level is a level-two (L2) cache.
13 . The system of claim 11 , wherein:
the first cache memory is a main storage; and
the second cache memory is a victim storage.
14 . The system of claim 11 , wherein the first cache level comprises a store queue coupled to the second cache memory, and wherein the data of the pending write operation is stored in the store queue.
15 . The system of claim 11 , wherein:
the first cache level comprises a tag random access memory; and
the cache controller is capable of determining whether the read operation corresponds to a hit in the second cache memory based on content of the tag random access memory.
16 . The system of claim 11 , wherein the cache controller is capable of:
based on determining that there is no pending write operation directed to the address, obtaining data from the second cache memory; and
providing the data to the second cache level.
17 . The system of claim 11 , wherein the cache controller is capable of:
based on determining that the read operation corresponds to a hit in the second cache memory,
determining a modified, exclusive, shared, or invalid (MESI) state associated with the address of the second cache memory.
18 . The system of claim 17 , wherein:
the first cache level comprises a random access memory; and
wherein the cache controller is capable of determining the MESI state based on content of the random access memory.
19 . The system of claim 11 , wherein the cache controller is capable of:
based on determining that the read operation corresponds to a hit in the second cache memory, translating the address into an address space of the second cache memory.
20 . The system of claim 11 , wherein:
the first cache level comprises a first interface and a second interface; and
the first interface has a width larger than the second interface.