CIRCUITS AND METHODS TO HARVEST ENERGY FROM TRANSIENT ON-CHIP DATA
Circuits and methods that harvest electrostatic energy from transient on-chip data are described in the Application. In one aspect, a method inverter circuit harvests electrostatic charge held at its output node at an electric potential comparable to the power supply voltage rail to a common grid/node as the output makes a 0→1 logic transition. This charge harvested at a common gride/node can be used by circuits (described in applications 63/090,169, 63/139,744) to drive 0→1 logic transition at their output nodes at lower energy drain from the on-chip power grid than a conventional CMOS inverter would with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.
1 . An apparatus, comprising:
an inverter having an input terminal and an output terminal;
a first N-channel field effect transistor (NFET) and a first P channel field effect transistor (PFET) with their drain terminals shorted together at the output terminal of the inverter, a source terminal of the first NFET and a source terminal of the first PFET are connected to a ground and a power supply, respectively;
a second PFET having a source terminal and a drain terminal configured to couple the output terminal of the inverter to a harvest terminal whose capacitance holds harvested charge at a voltage lower than a voltage of the power supply;
the input terminal and the output terminal of the inverter, during operation, having electric potentials making full-swing transitions between the voltage of the power supply and a voltage of the ground, the input terminal of the inverter connected directly to a gate input terminal of the first PFET;
a second NFET having a gate input terminal configured to be driven by the input terminal of the inverter and having a source terminal and a drain terminal connected to the ground and the output terminal of the inverter, respectively; and
a 2-input gate with its inputs configured to be driven by the input terminal and the output terminal of the inverter, the 2-input gate having an output terminal configured to drive a gate input terminal of the second PFET and an input terminal of a delay element having an inverted output configured to drive the first NFET of the inverter.