IP Library Patent Application 19300956
Patent Application
App. No. 19/300,956

ADAPTIVE DEVICE DATA CORRECTION WITH INCREASED MEMORY FAILURE HANDLING

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Quick Facts
Patent No.
US None
App. No.
19/300,956
Abstract

An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to identify failed memory regions in a memory by a rank, bank, and device associated with the failed memory region, and provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory. Other embodiments are disclosed and claimed.

Claims (91)

1 .- 20 . (Canceled)

21 . An apparatus comprising:

memory organized as a plurality of ranks, wherein each rank of the plurality of ranks comprises a plurality of banks and a plurality of devices; and

circuitry to:

identify one or more failed ranks of the plurality of ranks,

identify one or more failed banks of the one or more failed ranks,

identify one or more failed devices of the one or more failed ranks,

identify a failed region based on the identified one or more failed ranks, one or more failed banks, and one or more failed devices,

maintain a data structure based on the identification of the failed region, and

perform dynamic bank virtual lock step device data correction based on the data structure.

22 . The apparatus of claim 21 , wherein the identification identifies:

a first bank group comprising one or more first banks of the plurality of banks, wherein each bank of the one or more first banks:

is identified as one of the one or more failed banks,

is of a rank of the plurality of ranks, and

comprises a respective failed region in a first device of the plurality of devices, wherein a maximum possible number of the one or more first banks is greater than two; and

a second bank group comprising one or more second banks of the plurality of banks, wherein each bank of the one or more second banks:

is of a rank of the plurality of ranks, and

comprises a respective non-failed region in a second device of the plurality of devices, wherein a maximum possible number of the one or more second banks is greater than two, and wherein each of the one or more second banks is to correspond to a respective bank of the one or more first banks.

23 . The apparatus of claim 22 , wherein in order to maintain the data structure based on the identification of the failed region, the circuitry is further to access an entry of the data structure, wherein the entry indicates a correspondence of the first bank group with the second bank group, and wherein the entry comprises:

a first field to provide a first list of the one or more first banks; and

a second field to provide a second list of the one or more second banks.

24 . The apparatus of claim 23 , wherein the entry omits any explicit identifier of a level of virtual lock step device data correction.

25 . The apparatus of claim 22 , wherein:

in order to identify the failed region, the circuitry is further to determine that a subsequent failed region in a first rank is in the first device and a different non-failed bank as a previously identified failed region in the data structure; and

in order to maintain the data structure based on the identification, the circuitry is further to identify a non-failed bank in a second rank of the memory, and update the data structure to add a bank of the subsequent failed region to the first bank group, and add the identified non-failed bank to the second bank group.

26 . The apparatus of claim 21 , wherein the circuitry is further to:

determine if a subsequent failed region in a first rank is in a different device and in an already failed bank as a previously identified failed region, and, if so determined:

set up device data correction for the subsequent failed region in a backup memory region of both the first rank and a second rank of the memory,

add an entry for the different device in the data structure, and

update the data structure to add a bank of the subsequent failed region and a bank of the backup memory region to bank group information for the added entry.

27 . The apparatus of claim 21 , wherein the circuitry is further to:

determine if a subsequent failed region in a first rank is in a different device and in a non-failed bank as a previously identified failed region; and, if so determined:

identify a non-failed bank in a second rank of the memory,

add an entry for the different device in the data structure, and

update the data structure to add a bank of the subsequent failed region and the non-failed bank to bank group information for the added entry.

28 . The apparatus of claim 22 , wherein:

a first rank of the memory comprises the one or more first banks; and

the circuitry is further to perform adaptive multiple device data correction for failed regions in four or more devices of the first rank of the memory by virtual lock step with one or more other ranks of the memory.

29 . The apparatus of claim 28 , wherein:

the data structure is a first data structure; and

the circuitry is further to:

maintain a second data structure for the adaptive multiple device data correction, wherein the second data structure comprises fields that indicate failed rank information and non-failed rank information;

determine that a clean bank is available for a bank-level virtual lock step device data correction and that the second data structure can support an entry for device data correction for a next subsequent failed region; and

on determining that the clean bank is available for the bank-level virtual lock step device data correction and that the second data structure can support the entry for device data correction for the next subsequent failed region:

add an entry for the failed region in the second data structure, and

update the second data structure to indicate a failed rank, a failed bank, and a failed device of the next subsequent failed region and a non-failed rank and non-failed bank of the clean bank.

30 . The apparatus of claim 21 , wherein the data structure comprises fields that indicate failed rank information and non-failed rank information.

31 . A method, comprising:

identifying one or more failed ranks of a plurality of ranks within a memory, wherein the memory is organized as the plurality of ranks, wherein each rank of the plurality of ranks comprises a plurality of banks and a plurality of devices,

identifying one or more failed banks of the one or more failed ranks,

identifying one or more failed devices of the one or more failed ranks,

identifying a failed region based on the identified one or more failed ranks, one or more failed banks, and one or more failed devices,

maintaining a data structure based on the identification of the failed region, and

performing dynamic bank virtual lock step device data correction based on the data structure.

32 . The method of claim 31 , wherein the identifying identifies:

a first bank group comprising one or more first banks of the plurality of banks, wherein each bank of the one or more first banks:

is identified as one of the one or more failed banks,

is of a rank of the plurality of ranks, and

comprises a respective failed region in a first device of the plurality of devices, wherein a maximum possible number of the one or more first banks is greater than two; and

a second bank group comprising one or more second banks of the plurality of banks, wherein each bank of the one or more second banks:

is of a rank of the plurality of ranks, and

comprises a respective non-failed region in a second device of the plurality of devices, wherein a maximum possible number of the one or more second banks is greater than two, and wherein each of the one or more second banks is to correspond to a respective bank of the one or more first banks.

33 . The method of claim 32 , wherein in order to maintain the data structure based on the identifying of the failed region, the method further comprises accessing an entry of the data structure, wherein the entry indicates a correspondence of the first bank group with the second bank group, and wherein the entry comprises:

a first field to provide a first list of the one or more first banks; and

a second field to provide a second list of the one or more second banks.

34 . The method of claim 33 , wherein the entry omits any explicit identifier of a level of virtual lock step device data correction.

35 . The method of claim 32 , wherein:

in order to identify the failed region, the method further comprises determining that a subsequent failed region in a first rank is in the first device and a different non-failed bank as a previously identified failed region in the data structure; and

in order to maintain the data structure based on the identification, the method further comprises identifying a non-failed bank in a second rank of the memory, and updating the data structure to add a bank of the subsequent failed region to the first bank group, and adding the identified non-failed bank to the second bank group.

36 . The method of claim 31 , wherein the method further comprises:

determining if a subsequent failed region in a first rank is in a different device and in an already failed bank as a previously identified failed region, and, if so determined:

setting up device data correction for the subsequent failed region in a backup memory region of both the first rank and a second rank of the memory,

adding an entry for the different device in the data structure, and

updating the data structure to add a bank of the subsequent failed region and a bank of the backup memory region to bank group information for the added entry.

37 . The method of claim 31 , wherein the method further comprises:

determining if a subsequent failed region in a first rank is in a different device and in a non-failed bank as a previously identified failed region; and, if so determined:

identifying a non-failed bank in a second rank of the memory,

adding an entry for the different device in the data structure, and

updating the data structure to add a bank of the subsequent failed region and the non-failed bank to bank group information for the added entry.

38 . The method of claim 32 , wherein:

a first rank of the memory comprises the one or more first banks; and

the method further comprises performing adaptive multiple device data correction for failed regions in four or more devices of the first rank of the memory by virtual lock step with one or more other ranks of the memory.

39 . The method of claim 38 , wherein:

the data structure is a first data structure; and

the method further comprises:

maintaining a second data structure for the adaptive multiple device data correction, wherein the second data structure comprises fields that indicate failed rank information and non-failed rank information;

determining that a clean bank is available for a bank-level virtual lock step device data correction and that the second data structure can support an entry for device data correction for a next subsequent failed region; and

on determining that the clean bank is available for the bank-level virtual lock step device data correction and that the second data structure can support the entry for device data correction for the next subsequent failed region:

adding an entry for the failed region in the second data structure, and

updating the second data structure to indicate a failed rank, a failed bank, and a failed device of the next subsequent failed region and a non-failed rank and non-failed bank of the clean bank.

40 . The method of claim 31 , wherein the data structure comprises fields that indicate failed rank information and non-failed rank information.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2025
From: CHEN, LEI; LING, LIYANG; QIU, XIAODONG; JIANG, YONG
To: INTEL CORPORATION
Reel/Frame 072859/0752 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072549/0289 →