UNLOADED CACHE BYPASS

1 . A system, comprising:

a memory device; and

a memory controller coupled to the memory device and comprising:

a cache including a metric logic configured to track a quantity of pending cache look-up operations in a queue of the cache; and

a cache sequence controller coupled to the cache and configured to:

compare the quantity of pending cache look-up operations to a threshold quantity responsive to receiving a read request from a host, wherein the threshold is varied based on a cache hit rate of cache look-up operations; and

cause performance of a bypass read operation that bypasses the cache and accesses the memory device responsive to determining the quantity is less than or equal to the threshold.

2 . The system of claim 1 , wherein:

the threshold is decreased based on the cache hit rate being above a target hit rate; and

the threshold is increased based on the cache hit rate being below a target hit rate.

3 . The system of claim 1 , wherein the memory controller is configured to cause performance of a cache look-up operation associated with the cache substantially contemporaneously with the performance of the bypass read operation.

4 . The system of claim 3 , wherein performance of the cache look-up operation results in a cache hit, and wherein the memory controller is configured to discard data read from the memory device in association with the bypass read operation.

5 . The system of claim 3 , wherein performance of the cache look-up operation results in a cache miss.

6 . The system of claim 5 , wherein the cache miss is a clean cache miss, and wherein the cache sequence controller is further to cache-in data read from the memory device in association with the bypass read operation.

7 . The system of claim 5 , wherein the cache miss is a dirty cache miss, and wherein:

the cache sequence controller is configured to cache-in data read from the memory device in association with the bypass read operation; and

the memory controller is configured to cause performance of a cache write-back operation to write data from the cache to the memory device.

8 . The system of claim 1 , wherein the metric logic including counters, and wherein the counters comprise a cache hit counter, write hit counter, or a combination thereof.

9 . The system of claim 1 , wherein the cache further comprises a cache memory and a cache controller.

10 . The system of claim 1 , wherein the cache sequence controller is configured to cause performance of a cache look-up operation responsive to determining the quantity exceeds the threshold.

11 . The system of claim 10 , wherein the cache sequence controller is configured to continue causing performance of cache look-up operations responsive to receiving subsequent read requests from the host until the quantity of pending cache look-up operations is less than an exit threshold.

12 . A method, comprising:

determining, by a memory controller coupled to a memory device, a quantity of pending cache look-up operations in a queue associated with a cache responsive to receiving a host access request;

determining the quantity of pending cache look-up operations is less than or equal to a threshold that is variable based on a cache hit rate of cache look-up operations; and

responsive to determining the quantity of pending cache look-up operations is less than or equal to the threshold:

causing performance of a bypass read operation that bypasses the cache and accesses the memory device; and

causing performance of a cache look-up operation substantially contemporaneously with the performance of the bypass read operation.

13 . The method of claim 12 , wherein data associated with the performance of the bypass read operation is selectively utilized based on a type of result of the cache look-up operation.

14 . The method of claim 12 , wherein the threshold is equal to a non-zero quantity of pending cache look-up operations.

15 . The method of claim 12 , wherein the threshold is equal to zero pending cache look-up operations.

16 . An apparatus, comprising:

a memory device; and

a memory controller coupled to the memory device and comprising:

a cache including a metric logic configured to track a quantity of pending cache look-up operations in a queue of the cache; and

a cache sequence controller coupled to the cache and configured to:

responsive to receiving a host read request:

determine that the quantity of pending cache look-up operations satisfies a variable unloaded bypass threshold, wherein the variable unloaded bypass threshold is varied based on a cache hit rate of cache look-up operations;

cause performance of a cache look-up operation; and

in parallel with performance of the cache look-up operation, cause initiation of a bypass read operation that bypasses the cache and accesses the memory device to read data corresponding to the host read request from the memory device.

17 . The apparatus of claim 16 , wherein the cache is configured to operate in accordance with a First-in First-out (FIFO) cache replacement policy.

18 . The apparatus of claim 16 , wherein the cache sequence controller is to cause performance of a plurality of bypass read operations when the quantity of the pending cache look-up operations in the queue is less than or equal to the variable unloaded bypass threshold.

19 . The apparatus of claim 16 , further comprising an exit threshold that is less than the variable unloaded bypass threshold, wherein the cache sequence controller is to abstain from performance of any bypass read operation until the quantity of the pending look-up operations is less than the exit threshold.

20 . The apparatus of claim 16 , wherein:

the variable unloaded bypass threshold is decreased based on the cache hit rate being above a target hit rate; and

the variable unloaded bypass threshold is increased based on the cache hit rate being below a target hit rate.