MECHANISMS FOR FABRICATING MICRO-LEDS
In some embodiments, methods for fabricating micro-LEDs may include bonding a semiconductor wafer to a Complementary Metal-Oxide-Semiconductor (CMOS) wafer via one or more adhesive layers, etching the LED epilayer and the one or more adhesive layers to form a plurality of micro-LED structures, and fabricating an electrode layer on the plurality of microLED structures. The semiconductor wafer may include an LED epilayer that may include an n-GaN layer, a p-GaN layer, and an active layer positioned between the n-GaN layer and the p-GaN layer. The stress release pattern may include a plurality of geometrical shapes (e.g., squares, rectangles, hexagons, rings, etc.) that may facilitate the release of mechanical stresses induced during the subsequent processing of the semiconductor wafer and/or the fabrication of the micro-LEDs.
1 . A method, comprising:
bonding a semiconductor wafer to a Complementary Metal-Oxide-Semiconductor (CMOS) wafer via one or more adhesive layers, wherein the semiconductor wafer comprises an LED epilayer;
fabricating a stress release pattern that divides the LED epilayer into a plurality of portions; and
etching the LED epilayer and the one or more adhesive layers to form a plurality of micro-LED structures.
2 . The method of claim 1 , wherein fabricating the stress release pattern in the semiconductor wafer comprises etching at least a portion of the LED epilayer.
3 . The method of claim 2 , wherein the semiconductor wafer further comprises a first substrate, and wherein the method further comprises removing the first substrate to expose a surface of the LED epilayer prior to fabricating the stress release pattern.
4 . The method of claim 3 , wherein a dimension of the first substrate is equal to or greater than 2 inches.
5 . The method of claim 1 , wherein the CMOS wafer comprises a second substrate and a plurality of interconnects formed on the second substrate, and wherein bonding the semiconductor wafer to the CMOS wafer via the one or more adhesive layers comprises coating one or more bonding materials on the LED epilayer and the interconnects.
6 . The method of claim 5 , wherein the plurality of interconnects comprises a plurality of metallic pads or a plurality of metallic vias.
7 . The method of claim 5 , wherein each of the plurality of micro-LED structures is fabricated on a respective interconnect of the plurality of interconnects.
8 . The method of claim 5 , wherein a dimension of the second substrate is equal to or greater than 2 inches.
9 . The method of claim 1 , further comprising fabricating an electrode layer on the plurality of micro-LED structures.
10 . The method of claim 9 , further comprising fabricating a dielectric layer on the plurality of micro-LED structures, wherein the electrode layer is fabricated on the dielectric layer and the plurality of micro-LED structures.
11 . The method of claim 10 , wherein fabricating the electrode layer comprises fabricating a layer of a conductive material on the dielectric layer and top surfaces of the plurality of microLED structures.
12 . The method of claim 1 , wherein the LED epilayer comprises a plurality of epitaxial layers of gallium nitride.
13 . The method of claim 1 , wherein the stress release pattern comprises one or more geometrical shapes that divide the LED epilayer into a plurality of segments.
14 . The method of claim 1 , wherein the stress release pattern is fabricated after bonding the semiconductor wafer and the CMOS wafer.