MANAGING ERROR CONTROL INFORMATION USING A REGISTER
Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.
1 . (canceled)
2 . A memory device, comprising:
storage circuitry operable to store data received at the memory device;
first circuitry operable to generate first information associated with an error control operation based at least in part on the received data;
second circuitry operable to generate second information associated with the error control operation based at least in part on retrieving the data from the storage circuitry;
match circuitry operable to receive the first information and the second information from the first circuitry and the second circuitry, compare the first information and the second information, and output a signal indicative of whether the first information matches the second information based at least in part on comparing the first information and the second information; and
a register operable to receive the signal from the match circuitry and store an indication of whether the first information matches the second information based at least in part on receiving the signal.
3 . The memory device of claim 2 , wherein the match circuitry is operable to compare the first information and the second information based at least in part on performing one or more exclusive or (XOR) operations on respective bits of the first information and the second information.
4 . The memory device of claim 2 , wherein the match circuitry is operable to:
output a quantity of zero values based at least in part on each bit of the first information matching a corresponding bit of the second information; or
output one or more non-zero values based at least in part on one or more bits of the first information failing to match a corresponding bit of the second information.
5 . The memory device of claim 4 , wherein, to output the signal, the match circuitry is operable to:
output a first signal indicating a match based at least in part on a quantity of non-zero values output by the match circuitry failing to satisfy a threshold quantity; or
output a second signal indicating a mismatch based at least in part on the quantity of non-zero values satisfying the threshold quantity.
6 . The memory device of claim 4 , wherein one or more outputs of the match circuitry are indicative of a position of one or more corrupted bits in the data stored at the storage circuitry or in the first information based at least in part on outputting the one or more non-zero values.
7 . The memory device of claim 2 , wherein the signal comprises a Boolean false value indicating a match, or a Boolean true value indicating a mismatch.
8 . The memory device of claim 2 , wherein the first circuitry is operable to generate the first information and the second circuitry is operable to generate the second information based at least in part on a same algorithm.
9 . The memory device of claim 2 , wherein the first information comprises a first plurality of syndromes and the second information comprises a second plurality of syndromes.
10 . A method by a memory device, comprising:
receiving, at the memory device, data;
storing, at storage circuitry of the memory device, the data received at the memory device;
generating, using first circuitry of the memory device, first information associated with an error control operation based at least in part on the received data;
generating, using second circuitry of the memory device, second information associated with the error control operation based at least in part on retrieving the data from the storage circuitry;
comparing, using match circuitry of the memory device based at least in part on receiving the first information and the second information at the match circuitry, the first information and the second information;
outputting, from the match circuitry, a signal indicative of whether the first information matches the second information based at least in part on comparing the first information and the second information; and
storing, at a register of the memory device based at least in part on receiving the signal at the register, an indication of whether the first information matches the second information.
11 . The method of claim 10 , wherein comparing the first information and the second information is based at least in part on performing one or more exclusive or (XOR) operations on respective bits of the first information and the second information.
12 . The method of claim 10 , further comprising:
outputting, from the match circuitry, a quantity of zero values based at least in part on each bit of the first information matching a corresponding bit of the second information; or
outputting, from the match circuitry, one or more non-zero values based at least in part on one or more bits of the first information failing to match a corresponding bit of the second information.
13 . The method of claim 12 , wherein outputting the signal comprises:
outputting a first signal indicating a match based at least in part on a quantity of non-zero values output by the match circuitry failing to satisfy a threshold quantity; or
outputting a second signal indicating a mismatch based at least in part on the quantity of non-zero values satisfying the threshold quantity.
14 . The method of claim 12 , wherein one or more outputs of the match circuitry are indicative of a position of one or more corrupted bits in the data stored at the storage circuitry or in the first information based at least in part on outputting the one or more non-zero values.
15 . The method of claim 10 , wherein the signal comprises a Boolean false value indicating a match, or a Boolean true value indicating a mismatch.
16 . The method of claim 10 , wherein generating the first information and generating the second circuitry are based at least in part on a same algorithm.
17 . The method of claim 10 , wherein the first information comprises a first plurality of syndromes and the second information comprises a second plurality of syndromes.
18 . A non-transitory computer-readable medium storing code for operating a memory device, the code comprising instructions executable by one or more processors to:
receive, at the memory device, data;
store, at storage circuitry of the memory device, the data received at the memory device;
generate, using first circuitry of the memory device, first information associated with an error control operation based at least in part on the received data;
generate, using second circuitry of the memory device, second information associated with the error control operation based at least in part on retrieving the data from the storage circuitry;
compare, using match circuitry of the memory device based at least in part on receiving the first information and the second information at the match circuitry, the first information and the second information;
output, from the match circuitry, a signal indicative of whether the first information matches the second information based at least in part on comparing the first information and the second information; and
store, at a register of the memory device based at least in part on receiving the signal at the register, an indication of whether the first information matches the second information.
19 . The non-transitory computer-readable medium of claim 18 , wherein comparing the first information and the second information is based at least in part on performing one or more exclusive or (XOR) operations on respective bits of the first information and the second information.
20 . The non-transitory computer-readable medium of claim 18 , wherein the instructions are further executable by the one or more processors to:
output a quantity of zero values based at least in part on each bit of the first information matching a corresponding bit of the second information; or
output one or more non-zero values based at least in part on one or more bits of the first information failing to match a corresponding bit of the second information.
21 . The non-transitory computer-readable medium of claim 20 , wherein, to output the signal, the instructions are executable by the one or more processors to:
output a first signal indicating a match based at least in part on a quantity of non-zero values output by the match circuitry failing to satisfy a threshold quantity; or
output a second signal indicating a mismatch based at least in part on the quantity of non-zero values satisfying the threshold quantity.