BUFFER EXPANSION FOR RANDOM WRITE OPERATIONS
Methods, systems, and devices for buffer expansion for random write operations are described. Implementations provide buffer expansion for random write operations used to store L2P address translation table data under certain recognized operation workloads. Memory locations within the memory system controller are typically allocated for use during various operations. During different operational workloads, the amount of memory required for each of these different allocated memory areas may vary. By recognizing the entry of the memory system into a workload of random write operations, the memory system controller may expand a buffer size used to store the portion of the L2P address translation table data used during the write operations to retain larger portions of the L2P address translation table in the buffer.
1 . (canceled)
2 . A memory system, comprising:
a non-volatile memory; and
one or more controllers comprising a volatile memory, wherein the one or more controllers are configured to cause the memory system to:
receive a plurality of write commands associated with a plurality of logical addresses; and
allocate, for a duration based at least in part on the plurality of write commands comprising random write commands, a plurality of volatile memory cells of the volatile memory to use as a buffer for storing mapping information between the plurality of logical addresses and a plurality of physical addresses for the non-volatile memory, wherein allocating the plurality of volatile memory cells increases a size of the buffer from a first size to a second size.
3 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
update, at a second buffer, a change-log of entries that include changes to mappings, of an address mapping table, between the plurality of logical addresses and the plurality of physical addresses based at least in part on receiving the plurality of write commands.
4 . The memory system of claim 3 , wherein the one or more controllers are further configured to cause the memory system to:
determine that a quantity of the entries of the change-log satisfies a threshold value; and
update, at the buffer based at least in part on the change-log in the second buffer, the mapping information between the plurality of logical addresses and the plurality of physical addresses based at least in part on the quantity of the entries of the change-log satisfying a threshold value.
5 . The memory system of claim 4 , wherein the one or more controllers are further configured to cause the memory system to:
transfer the updated mapping information from the buffer to the non-volatile memory based at least in part on the quantity of the entries of the change-log satisfying the threshold value.
6 . The memory system of claim 5 , wherein the second buffer comprises a second plurality of volatile memory cells, independent from the plurality of volatile memory cells, for storing the entries of the change-log, and wherein transferring the updated mapping information to the non-volatile memory occurs during the duration.
7 . The memory system of claim 4 , wherein the one or more controllers are further configured to cause the memory system to:
determine that the quantity of the entries in the change-log satisfies the threshold value based at least in part on updating the change-log.
8 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
allocate, after the duration, the plurality of volatile memory cells to use as a second buffer for storing information other than the mapping information.
9 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
transfer the mapping information stored in the buffer to the non-volatile memory based at least in part on a quantity of data written to the non-volatile memory satisfying a threshold value.
10 . The memory system of claim 9 , wherein the one or more controllers are further configured to cause the memory system to:
update, at the buffer, the mapping information between the plurality of logical addresses and the plurality of physical addresses; and
determine that the quantity of data written to the non-volatile memory satisfies the threshold value based at least in part on updating the mapping information.
11 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
receive a second plurality of write commands associated with a second plurality of logical addresses; and
determine, based at least in part on the second plurality of logical addresses, that the second plurality of write commands comprise non-random write commands.
12 . The memory system of claim 11 , wherein the one or more controllers are further configured to cause the memory system to:
de-allocate, based at least in part on the second plurality of write commands comprising non-random write commands, the plurality of volatile memory cells of the volatile memory from use as the buffer, wherein de-allocating the plurality of volatile memory cells decreases the size of the buffer.
13 . A memory system, comprising:
a non-volatile memory; and
one or more controllers comprising a volatile memory, wherein the one or more controllers are configured to cause the memory system to:
receive a plurality of write commands associated with a plurality of logical addresses; and
de-allocate, based at least in part on the plurality of write commands comprising non-random write commands, a plurality of volatile memory cells of the volatile memory from use as a buffer for storing mapping information between the plurality of logical addresses and a plurality of physical addresses for the non-volatile memory, wherein de-allocating the plurality of volatile memory cells decreases a size of the buffer from a first size to a second size.
14 . The memory system of claim 13 , wherein the one or more controllers are further configured to cause the memory system to:
determine, based at least in part on a second plurality of logical addresses associated with a second plurality of write commands, that the second plurality of write commands comprise random write commands; and
allocate, based at least in part on determining that the second plurality of write commands comprise random write commands, the plurality of volatile memory cells to use as the buffer, wherein allocating the plurality of volatile memory cells increases the size of the buffer.
15 . The memory system of claim 14 , wherein the one or more controllers are further configured to cause the memory system to:
update, at a second buffer, a change-log of entries that include changes to mappings, of an address mapping table, between the second plurality of logical addresses and a second plurality of physical addresses based at least in part on receiving the second plurality of write commands.
16 . The memory system of claim 15 , wherein the one or more controllers are further configured to cause the memory system to:
determine that a quantity of the entries of the change-log satisfies a threshold value; and
update the mapping information at the buffer based at least in part on the quantity of the entries of the change-log satisfying the threshold value.
17 . The memory system of claim 16 , wherein the one or more controllers are further configured to cause the memory system to:
transfer the updated mapping information from the buffer to the non-volatile memory based at least in part on the quantity of the entries of the change-log satisfying the threshold value.
18 . The memory system of claim 17 , wherein the one or more controllers are further configured to cause the memory system to:
determine that the quantity of the entries in the change-log satisfies the threshold value based at least in part on updating the change-log.
19 . The memory system of claim 13 , wherein the one or more controllers are further configured to cause the memory system to:
allocate, based at least in part on de-allocating the plurality of volatile memory cells, the plurality of volatile memory cells to use as a second buffer for storing information other than mapping information.
20 . The memory system of claim 13 , wherein the one or more controllers are further configured to cause the memory system to:
allocate, based at least in part on de-allocating the plurality of volatile memory cells, the plurality of volatile memory cells to use as a second buffer for storing data read from the memory system or for storing write data for writing to the memory system.
21 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of a memory system, cause the memory system to:
receive a plurality of write commands associated with a plurality of logical addresses; and
allocate, for a duration based at least in part on the plurality of write commands comprising random write commands, a plurality of volatile memory cells of a volatile memory to use as a buffer for storing mapping information between the plurality of logical addresses and a plurality of physical addresses for a non-volatile memory, wherein allocating the plurality of volatile memory cells increases a size of the buffer from a first size to a second size.