SELECTIVE CAVITY MERGING FOR ISOLATION REGIONS IN A MEMORY DIE
Methods, systems, and devices for selective cavity merging for isolation regions in a memory die are described. For example, formation of material structures of a memory die may include depositing a stack of alternating layers of a first material and a second material over a substrate of the memory die, forming a pattern of cavities through the stack of alternating material layers, and forming voids between layers of the first material based on removing portions of the second material. An electrical isolation region may be formed between portions of the memory die based on depositing a dielectric material in at least some of the cavities and in at least a portion of the voids between the layers of the first material.
1 . (canceled)
2 . An apparatus, comprising:
a first array region of a memory die comprising a plurality of first memory cells and a plurality of first access lines coupled with the plurality of first memory cells, the plurality of first access lines arranged between a plurality of layers of a first dielectric material in the first array region;
a second array region of the memory die comprising a plurality of second memory cells and a plurality of second access lines coupled with the plurality of second memory cells, the plurality of second access lines arranged between the plurality of layers of the first dielectric material in the second array region; and
an electrical isolation between the first array region and the second array region, the electrical isolation comprising first portions of a second dielectric material between the plurality of layers of the first dielectric material and between the plurality of first access lines and the plurality of second access lines, and second portions of the second dielectric material within sidewalls of the first dielectric material through each layer of the plurality of layers of the first dielectric material.
3 . The apparatus of claim 2 , wherein the second dielectric material is in contact with the plurality of first access lines, the plurality of second access lines and the sidewalls of the first dielectric material.
4 . The apparatus of claim 2 , wherein the second dielectric material is the same as the first dielectric material.
5 . The apparatus of claim 2 , wherein the first portions of the second dielectric material and the second portions of the second dielectric material are contiguous with one another.
6 . The apparatus of claim 2 , wherein each sidewall of one layer of the first dielectric material is concentric with a sidewall of each other layer of the first dielectric material.
7 . The apparatus of claim 2 , wherein one of the sidewalls of a first layer of the first dielectric material encloses a first cross-sectional area, and wherein one of the sidewalls of a second layer of the first dielectric material, between the first layer and a substrate, encloses a second cross-sectional area that is smaller than the first cross-sectional area.
8 . The apparatus of claim 2 , wherein, for each layer of the plurality of layers of the first dielectric material, the sidewalls are arranged along one or more rows between the first array region and the second array region.
9 . The apparatus of claim 2 , wherein the first dielectric material comprises an oxide of silicon.
10 . The apparatus of claim 2 , wherein the plurality of first access lines and the plurality of second access lines each comprise tungsten.
11 . The apparatus of claim 2 , wherein the second portions of the second dielectric material comprise:
a plurality of first sets of second portions, each first set of the plurality of first sets having a first taper along a direction toward a substrate of the memory die; and
a plurality of second sets of second portions, each second set of the plurality of second sets aligned with a respective one of the plurality of first sets and having a second taper along the direction toward the substrate of the memory die.
12 . The apparatus of claim 2 , wherein plurality of layers of first dielectric material comprise portions that are continuous between the first array region and the second array region across the electrical isolation region.
13 . An apparatus formed by a process comprising:
depositing a stack of material layers over a substrate of a memory die, the stack of material layers comprising alternating layers of a first material and a second material;
forming a plurality of cavities through the stack of material layers;
forming one or more voids between the layers of the first material based at least in part on removing one or more portions of the second material; and
forming an electrical isolation region between a first portion of the memory die and a second portion of the memory die based at least in part on depositing a dielectric material in the plurality of cavities and in the one or more voids between the layers of the first material.
14 . The apparatus of claim 13 , wherein depositing the dielectric material comprises:
depositing the dielectric material in portions of the one or more voids between the layers of the first material that extend between adjacent cavities of the plurality of cavities.
15 . The apparatus of claim 13 , wherein the first portion of the memory die comprises a first block of memory cells and the second portion of the memory die comprises a second block of memory cells.
16 . The apparatus of claim 15 , formed by the process further comprising:
forming one or more first access lines for the first block of memory cells based at least in part on depositing one or more conductive materials in portions of the one or more voids between the layers of the first material in the first portion of the memory die; and
forming one or more second access lines for the second block of memory cells based at least in part on depositing the one or more conductive materials in portions of the one or more voids between the layers of the first material in the second portion of the memory die.
17 . The apparatus of claim 16 , wherein the one or more first access lines and the one or more second access lines are electrically isolated from one another based at least in part on depositing the dielectric material in the plurality of cavities and in the one or more voids between the layers of the first material.
18 . The apparatus of claim 15 , formed by the process further comprising:
forming the first block of memory cells based at least in part on depositing a second dielectric material and a semiconductor material in a plurality of second cavities in the first portion of the memory die; and
forming the second block of memory cells based at least in part on depositing the second dielectric material and the semiconductor material in a plurality of third cavities in the second portion of the memory die.
19 . The apparatus of claim 18 , formed by the process further comprising:
forming the plurality of second cavities and the plurality of third cavities through the stack of material layers concurrently with forming the plurality of cavities through the stack of material layers.
20 . The apparatus of claim 13 , wherein the plurality of cavities are formed via cross-sectional openings that are non-overlapping with one another.
21 . The apparatus of claim 13 , wherein the dielectric material is the same as the first material.