REDUCED POWER ADDRESSING
An intermediate component can be provided between initiator components (from which access requests are originated) and target components (that are to be accessed via the access requests). The intermediate component can encode, decode, and/or bypass the encoding process of address bits to ensure that address bits of the access requests are in a format that is compatible with access of the respective target component.
1 . An apparatus, comprising:
an encoder configured to convert a set of address bits of an access request from a first format to a second format, the second format corresponding to a reduced-Hamming-distance binary code that reduces toggles relative to the first format; and
a selection component configured to:
receive a plurality of access requests including the access request, the plurality of access requests further including at least two access requests of the plurality of access requests from different address encoders; and
selectively transfer one of the plurality of access requests to a target component to access the target component via execution of the one of the plurality of access requests.
2 . The apparatus of claim 1 , wherein the selection component comprises a selector, a multiplexer, an arbiter, or any combination thereof.
3 . The apparatus of claim 1 , wherein the selection component is configured to incorporate priority management, quality of service control, security measures, rule-based arbitration, access control, or any combination thereof.
4 . The apparatus of claim 1 , wherein the selection component comprises a buffer that is configured to store one or more commands and/or data associated with the plurality of access requests.
5 . The apparatus of claim 1 , wherein the selection component is part of an intermediate component further comprising interconnects, one or more buses, transmission lines, or any combination thereof.
6 . The apparatus of claim 5 , wherein the interconnects comprise a Network-on-Chip (NOC), a fabric interconnect, a ring interconnect, a bus interconnect, or any combination thereof.
7 . The apparatus of claim 1 , wherein the target component comprises an interconnect, fabric, crossbar, network on a chip, intellectual property (IP) core, partition, domain, module, or structure that is sequentially addressed.
8 . The apparatus of claim 1 , wherein address bits of at least two access requests of the plurality of access requests have different formats.
9 . The apparatus of claim 1 , wherein the target component is an initiator port, a loopback port, an input/output (I/O) port of an initiator connector.
10 . An apparatus, comprising:
an encoder configured to convert a first set of address bits of a first access request from a first format to a second format, the second format corresponding to a reduced-Hamming-distance binary code that reduces toggles relative to the first format; and
a selection component configured to:
receive a plurality of access requests including the first access request, the plurality of access requests further including at least two access requests of the plurality of access requests having different formats; and
selectively transfer one of the plurality of access requests to a target component to access the target component via execution of the one of the plurality of access requests.
11 . The apparatus of claim 10 , wherein at least two access requests of the plurality of access requests are received from different address encoders.
12 . The apparatus of claim 10 , wherein the second format comprises a reflected binary code (RBC) format, a Johnson ring (cyclic) code format, or a unit-distance binary code in which two successive binary values differ in a single bit position.
13 . The apparatus of claim 10 , wherein the first format comprises a binary code format that is not tailored to reduce a Hamming distance.
14 . The apparatus of claim 10 , further comprising an address decoder configured to convert a format of encoded address bits from the second format back to the first format prior to selectively transferring the one of the plurality of access requests to a particular target component that is not compatible with access via address bits having the second format.
15 . The apparatus of claim 10 , wherein the selection component is configured to provide a bypass mechanism in which at least one access request with address bits having the first format is transferred to a particular target component as is when the particular target component is not compatible with access via address bits having the second format.
16 . The apparatus of claim 10 , wherein the encoder is configured to selectively not convert a portion of the first set of address bits, one or more bits of the portion of the first set indicative of which byte within the first set of address bits is to be accessed.
17 . The apparatus of claim 16 , wherein the first set of address bits further comprises:
a first portion of the first set of address bits corresponding to a first byte address; and
a second portion of the first set of address bits corresponding to a second byte address.
18 . The apparatus of claim 10 , wherein the encoder is configured to:
selectively refrain from converting a portion of the first set of address bits, such that the portion remains in the first format, based on whether an encoded value would exceed a limit of a target address space of the target component.
19 . A method, comprising:
receiving a plurality of access requests including a first access request for a first target component, the plurality of access requests further including at least two access requests of the plurality of access requests from different address encoders, wherein:
a format of the first access request is converted from a first format to a second format; and
the second format corresponds to a reduced-Hamming-distance binary code that reduces toggles relative to the first format; and
selectively transferring one of the plurality of access requests to the first target component to access the first target component via execution of the one of the plurality of access requests.
20 . The method of claim 19 , further comprising, responsive to receiving a second access request to access a second target component that is not compatible with access via address bits having the second format, transferring the second access request with address bits having the first format as is to cause the second access request to be executed with the address bits in the first format.