ERASE PULSE LOOP DEPENDENT ADJUSTMENT OF SELECT GATE ERASE BIAS VOLTAGE
Control logic of a memory device initiates an erase operation including a set of erase loops to erase one or more memory cells. During a first erase loop, a first erase pulse having an erase voltage level is applied to a source line associated with the one or more memory cells. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is applied to the source line to ramp a voltage of the source line to a final erase voltage level, and an erase bias voltage is applied to a first select gate and a second select gate. In response to determining the voltage of the source line satisfies a condition, a first adjusted bias voltage is applied to the first select gate and a second adjusted erase bias voltage is applied to the second select gate.
1 . A memory device comprising:
an array of memory cells; and
control logic, operatively coupled with the array of memory cells, to perform operations comprising:
causing, during a first erase loop of an erase operation comprising a set of erase loops to erase one or more memory cells the array of memory cells, a first erase pulse having an erase voltage level to be applied to a source line associated with the one or more memory cells of the memory device; and
during a subset of erase loops following the first erase loop:
causing a second erase pulse having the erase voltage level to be applied to the source line to ramp a voltage of the source line to a final erase voltage level;
causing an erase bias voltage to be applied to a first select gate and a second select gate;
in response to determining the voltage of the source line satisfies a condition:
causing a first adjusted bias voltage to be applied to the first select gate; and
causing a second adjusted erase bias voltage to be applied to the second select gate.
2 . The memory device of claim 1 , wherein the condition is satisfied when the voltage of the source line reaches a criteria voltage level.
3 . The memory device of claim 2 , wherein the criteria voltage level is less than the final erase voltage level.
4 . The memory device of claim 1 , wherein the first adjusted bias voltage applied to the first select gate is determined by reducing the erase voltage level applied to the source line by a first adjusted delta voltage, and the second adjusted erase bias voltage applied to the second select gate is determined by reducing the erase voltage level applied to the source line by a second adjusted delta voltage that is less than the first adjusted delta voltage.
5 . The memory device of claim 4 , wherein the operations further comprise:
during the first erase loop, causing a first erase bias voltage having an initial voltage level to be applied to the first select gate and causing a second erase bias voltage having the initial voltage level to be applied to the second select gate, wherein the initial voltage level is equal to the erase voltage level reduced by an initial delta voltage level.
6 . The memory device of claim 5 , wherein the first adjusted delta voltage used to determine the first adjusted bias voltage is greater than the initial delta voltage level, and the second adjusted delta voltage used to determine the second adjusted erase bias voltage is greater than the initial delta voltage level.
7 . The memory device of claim 1 , wherein the first select gate comprises a source select gate that is adjacent to a source line that makes lateral contact with a pillar channel, and the second select gate is adjacent to the first select gate.
8 . The memory device of claim 1 , wherein the first adjusted bias voltage applied to the first select gate is lower than the second adjusted erase bias voltage applied to the second select gate.
9 . A memory device comprising:
an array of memory cells; and
control logic, operatively coupled with the array of memory cells, to perform operations comprising:
causing, during a first erase loop of an erase operation comprising a set of erase loops to erase one or more memory cells of the array of memory cells, a first erase pulse having an erase voltage level to be applied to a source line associated with the one or more memory cells of the memory device;
during the first erase loop, causing a first erase bias voltage to be applied to a first select gate and a second select gate; and
during a subset of erase loops following the first erase loop:
causing a second erase pulse having the erase voltage level to be applied to the source line; and
in response to determining a voltage of the source line satisfies a condition, causing a first adjusted erase bias voltage to be applied to the first select gate, wherein the first adjusted erase bias voltage is less than the erase voltage level.
10 . The memory device of claim 9 , wherein applying the first adjusted erase bias voltage to the first select gate reduces trap-up of hot electrons in an overlap region between the source line and the first select gate.
11 . The memory device of claim 9 , wherein, during the first erase loop, the first erase bias voltage is ramped with the erase voltage level applied to the source line.
12 . The memory device of claim 9 , wherein the operations further comprise causing, during the subset of erase loops following the first erase loop, a second adjusted erase bias voltage to be applied to the second select gate.
13 . The memory device of claim 12 , wherein the first adjusted erase bias voltage is less than the second adjusted erase bias voltage.
14 . The memory device of claim 12 , wherein the first adjusted erase bias voltage applied to the first select gate is determined by reducing the erase voltage level applied to the source line by a first adjusted delta voltage, and the second adjusted erase bias voltage applied to the second select gate is determined by reducing the erase voltage level applied to the source line by a second adjusted delta voltage that is less than the first adjusted delta voltage.
15 . The memory device of claim 9 , wherein the condition is satisfied when the voltage of the source line reaches a criteria voltage level.
16 . A memory device comprising:
an array of memory cells; and
control logic, operatively coupled with the array of memory cells, to perform operations comprising:
during each erase loop of a subset of erase loops following a first erase loop of an erase operation to erase one or more memory cells of the array of memory cells:
causing an erase pulse having an erase voltage level to be applied to a source line associated with the one or more memory cells to ramp a voltage of the source line to a final erase voltage level;
causing an erase bias voltage to be applied to a first select gate and a second select gate; and
in response to determining the voltage of the source line satisfies a condition:
causing a first adjusted bias voltage to be applied to the first select gate; and
causing a second adjusted erase bias voltage to be applied to the second select gate.
17 . The memory device of claim 16 , wherein the operations further comprise causing, during an erase loop executed prior to the subset of erase loops, a first erase pulse having an erase voltage level to be applied to the source line associated with the one or more memory cells of the memory device.
18 . The memory device of claim 16 , wherein the condition is satisfied when the voltage of the source line reaches a criteria voltage level.
19 . The memory device of claim 16 , wherein the first adjusted bias voltage applied to the first select gate is less than the second adjusted erase bias voltage applied to the second select gate.
20 . The memory device of claim 16 , wherein the first adjusted bias voltage is determined by reducing the erase voltage level by a first adjusted delta voltage, and the second adjusted erase bias voltage is determined by reducing the erase voltage level by a second adjusted delta voltage that is less than the first adjusted delta voltage.