MEMORY APPARATUS FOR PROVIDING RELIABILITY, AVAILABILITY, AND SERVICEABILITY
A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The memory system with such memory units implemented can still provide a degree of data integrity and/or data authenticity required by standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).
1 . An apparatus, comprising:
a Compute Express Link (CXL)-compliant memory system comprising:
a first number of memory units configured to store user data, at least one memory unit of the first number of memory units comprising:
a respective first portion comprising a number of data pins having a first type and configured to store a respective portion of the user data; and
a respective second portion comprising a number of data pins having a second type and configured to store auxiliary data to protect data integrity and authenticity of the user data; and
a second number of memory units configured to store parity data corresponding to the user data.
2 . The apparatus of claim 1 , wherein the CXL-compliant memory system further comprises:
a controller coupled to the first number of memory units and the second number of memory units via a first interface; and
the controller configured to communicate according to a peripheral component interconnect express (PCIe) via a second interface.
3 . The apparatus of claim 2 , wherein the user data is a portion of a data stripe, the data stripe corresponding to a unit of data transfer for performance of an error correction operation using the parity data.
4 . The apparatus of claim 3 , wherein the controller is configured to access the data stripe at least from the first number of memory units or the second number of memory units at a rate of twenty bits per each beat.
5 . The apparatus of claim 2 , wherein the first interface is configured to operate according to a double data rate (DDR) protocol.
6 . The apparatus of claim 2 , wherein the controller is configured to:
generate parity data corresponding to the user data in response to receipt of the user data via the second interface;
write the user data to the first number of memory units; and
write the parity data to the second number of memory units.
7 . The apparatus of claim 6 , wherein the controller is configured to, in response to receipt of a read command to access the user data:
access the user data and the parity data as a unit of read access.
8 . The apparatus of claim 6 , wherein the controller is configured to, in response to receipt of a read command to access the user data:
access the user data as a unit of read access; and
access the parity data in response to a determination that one or more errors within the user data are not correctable via the auxiliary data.
9 . The apparatus of claim 8 , wherein the parity data corresponds to Redundant Array of Independent Disks (RAID) parity data.
10 . The apparatus of claim 1 , wherein the auxiliary data comprises cyclic redundancy check (CRC) data.
11 . An apparatus, comprising:
a first number of memory units configured to store user data, at least one memory unit of the first number of memory units comprising:
a respective first portion comprising a number of data pins having a first type and configured to store a respective portion of the user data; and
a respective second portion comprising a number of data pins having a second type and configured to store auxiliary data to protect data integrity and authenticity of the user data; and
a second number of memory units configured to store parity data corresponding to the user data;
wherein the auxiliary data comprises error correction information to correct a particular quantity of bit errors in a portion of the parity data corresponding to a respective memory unit of the second number of memory units.
12 . The apparatus of claim 11 , wherein at least one memory unit of the first number of memory units or the second number of memory units does not include a dynamic voltage frequency scaling core (DVFSC) or a sub-threshold current reduce circuit (SCRC), or both.
13 . The apparatus of claim 11 , wherein at least one memory unit of the first number of memory units or the second number of memory units comprises an array of NAND memory cells.
14 . The apparatus of claim 11 , wherein at least one memory unit of the first number of memory units or the second number of memory units comprises an array of DRAM memory cells.
15 . The apparatus of claim 11 , wherein the auxiliary data comprises authentication data calculated based on trusted execution environment (TEE) data, host physical address (HPA), and a security key identifier (ID) associated with a particular location on which the user data is stored.
16 . An apparatus, comprising:
a first number of memory units configured to store user data, at least one memory unit of the first number of memory units comprising:
a respective first portion comprising a number of data pins having a first type and configured to store a respective portion of the user data; and
a respective second portion comprising a number of data pins having a second type and configured to store auxiliary data to protect data integrity and authenticity of the user data; and
a second number of memory units configured to store parity data corresponding to the user data, wherein at least one memory unit of the second number of memory units further comprises:
a respective first portion comprising a number of data pins having the first type and configured to store a respective portion of the parity data; and
a respective second portion comprising a number of data pins having the second type and configured to store auxiliary data corresponding to the parity data.
17 . The apparatus of claim 16 , wherein:
a data pin having the first type corresponds to a data input/output (DQ) bus; and
a data pin having the second type corresponds to a data mask inversion (DMI) pin.
18 . The apparatus of claim 16 , wherein each memory unit of the first number of memory units or the second number of memory units is configured to transfer four bits of data per each beat.
19 . The apparatus of claim 16 , wherein the first or the second number of memory units comprises a pair of linked memory units, the pair of memory units further comprising:
a first memory unit of the pair configured to transfer data via an external data link; and
a second memory unit of the pair coupled to the first memory unit via an internal data link.
20 . The apparatus of claim 19 , wherein the second memory unit of the pair is configured to transfer data to the first memory unit of the pair via the internal data link to cause the first memory unit of the pair to further transfer the data via the external data link.