SELF-CALIBRATION IN A MEMORY DEVICE
Systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. The semiconductor device receives an indication of a condition for re-training of the equalizer. The semiconductor device operates the equalizer based on trained values derived during the self-training. The semiconductor device also determines that the condition has been met, and in response, the semiconductor device re-trains the equalizer without invocation of re-training by a host device coupled to the semiconductor device.
1 . A method, comprising:
self-training an equalizer of a semiconductor device using the semiconductor device;
at the semiconductor device, receiving an indication of a condition upon which re-training of the equalizer is to be conducted;
operating the equalizer based on trained values derived during the self-training;
determining, using the semiconductor device, that the condition has been met; and
re-training the equalizer by the semiconductor device without invocation of re-training by a host device coupled to the semiconductor device, wherein re-training comprises re-training disabled memory ranks even while other memory ranks are active.
2 . The method of claim 1 , wherein the semiconductor device comprises a memory device.
3 . The method of claim 1 , wherein the equalizer is a decision feedback equalizer.
4 . The method of claim 1 , wherein the condition comprises a duration has elapsed since the self-training, a monitored temperature has crossed a threshold value, a voltage has varied in one direction over a period of time, a monitored voltage has crossed a voltage threshold value, or a combination thereof.
5 . The method of claim 1 , wherein re-training comprises determining voltage or current levels to be used in the equalizer.
6 . The method of claim 1 , wherein re-training comprises determining tap coefficients to be used in the equalizer.
7 . The method of claim 1 , wherein self-training comprises the host device initiating the self-training, but the semiconductor device handles the remaining portions of the self-training and re-training without supervision by the host device.
8 . The method of claim 1 , wherein re-training comprises continuous re-training.
9 . The method of claim 8 , wherein the condition comprises an indication that the re-training is to be continuous as long as the re-training is not disabled.
10 . A semiconductor device, comprising:
a receiver configured to receive data bits from another device and to latch at least some of the data bits in parallel in a first set of latches using a first reference voltage and in a second set of latches using a second reference voltage; and
self-calibration circuitry configured to increment a bit counter based on bit comparisons, comprising:
averaging circuitry comprising the bit counter configured to track a number of increments by the self-calibration circuitry, and the averaging circuitry is configured to track the number of the bit comparisons; and
adder/subtractor circuitry configured to add a value to or subtract the value from a present setting based on the number of increments counted to generate a new setting.
11 . The semiconductor device of claim 10 , wherein the semiconductor device comprises a memory device, the other device comprises a host device, and the self-calibration circuitry is configured to generate a first reference voltage without supervision from the host device.
12 . The semiconductor device of claim 10 , wherein incrementing the bit counter comprises determining to increment the bit counter based at least in part on a comparison of logic values of the parallel-latched bits.
13 . The semiconductor device of claim 10 , wherein the adder/subtractor circuitry is configured to receive a step size signal indicating the value to be added to or to be subtracted from the present setting to generate the new setting.
14 . The semiconductor device of claim 10 , wherein the semiconductor device comprises a memory device comprising a plurality of self-calibration circuitries including the self-calibration circuitry.
15 . The semiconductor device of claim 14 , comprising a plurality of data lines (DQ) that each correspond to a respective self-calibration circuitry of the plurality of self-calibration circuitries.
16 . The semiconductor device of claim 10 , wherein the averaging circuitry comprises a second bit counter configured to track the number of bit comparisons performed and to output a stop signal when the number of bit comparisons reaches a threshold number.
17 . The semiconductor device of claim 16 , wherein the threshold number is specified by the other device or indicated by one or more fuses of the semiconductor device.
18 . Self-calibration circuitry configured to perform self-training in a memory device, wherein the self-calibration circuitry comprises:
an input configured to receive first and second latched bits captured at the memory device and to increment a first bit counter based on a comparison of the first and second latched bits;
digital averaging circuitry comprising:
the first bit counter configured to track the number of increments determined; and
a second bit counter configured to track the number of bit comparisons performed; and
adder/subtractor circuitry configured to:
receive an indication of a previous setting of an equalizer; and
add an incremental value to or subtract the incremental value from the previous setting to output a new setting based at least in part on the indication of the previous setting and the number of increments counted in the first bit counter.
19 . The self-calibration circuitry of claim 18 , comprising a reference voltage generator, wherein the new setting comprises a digital code that the reference voltage generator is configured to translate into an analog voltage, and the reference voltage generator comprises a resistor ladder configured to selectively output different voltage levels as the reference voltage based on the digital code.
20 . The self-calibration circuitry of claim 19 , wherein the self-calibration circuitry is configured to determine tap settings of the equalizer using the new setting of the reference voltage using the digital averaging circuitry and the adder/subtractor circuitry.