DUAL INTERFACE HIGH-SPEED MEMORY SUBSYSTEM
A memory subsystem that includes a memory device, a first host interface, a serial interface controller that provides host access to a boot partition of the memory device using the first host interface, a second host interface, and a high-speed interface controller that provides host access to a user partition of the memory device using the second host interface.
1 . A method comprising:
responsive to power applied to a memory subsystem controller, transferring a primary boot loader from a memory device to a host system through a first, serial interface, wherein the memory subsystem includes a boot partition and a user partition and is coupled to the host system by the serial interface and a second, a high-speed interface, the serial interface providing the host system access to the boot partition, the high-speed interface providing the host system access to the user partition;
receiving, by the memory subsystem controller, a request from the host system for a second stage boot loader; and
responsive to the request, transferring, by the memory subsystem controller, the second stage boot loader from the memory device to the host system through the high-speed interface.
2 . The method of claim 1 , wherein the first interface is a Quad Serial Peripheral Interface (QSPI) interface.
3 . The method of claim 1 , wherein the second interface is one of a Peripheral Component Interconnect Express (PCIe), Serial Advanced Technology Attachment (SATA), and Unified Protocol (UniPro) interface.
4 . The method of claim 1 , further comprising:
setting timing settings for accessing the boot partition via the first interface.
5 . The method of claim 1 , wherein the primary boot loader is transferred before the second interface is initialized and available for transferring data from the memory device.
6 . The method of claim 1 , wherein the memory subsystem includes a serial interface controller that provides host access to the boot partition via the first interface and a high-speed interface controller that provides host access to the user partition via the second interface.
7 . The method of claim 6 , wherein the serial interface controller and the high-speed interface controller are initialized at least partly in parallel further in response to power being applied to the memory subsystem.
8 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
responsive to power applied to a memory subsystem controller, transfer a primary boot loader from a memory device to a host system through a first, serial interface, wherein the memory subsystem includes a boot partition and a user partition and is coupled to the host system by the serial interface and a second, high-speed interface, the serial interface providing the host system access to the boot partition and the high-speed interface providing the host system access to the user partition;
receive, by the memory subsystem controller, a request from the host system for a second stage boot loader; and
responsive to the request, transfer the second stage boot loader from the memory device to the host system through the high-speed interface.
9 . The non-transitory computer-readable storage medium of claim 8 , wherein the first interface is a Quad Serial Peripheral Interface (QSPI) interface.
10 . The non-transitory computer-readable storage medium of claim 8 , wherein the second interface is one of a Peripheral Component Interconnect Express (PCIe), Serial Advanced Technology Attachment (SATA), and Unified Protocol (UniPro) interface.
11 . The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:
set timing settings for accessing the boot partition via the first interface.
12 . The non-transitory computer-readable storage medium of claim 8 , wherein the primary boot loader is transferred before the second interface is initialized and available for transferring data from the memory device.
13 . The non-transitory computer-readable storage medium of claim 8 , wherein the memory subsystem includes a serial interface controller that provides host access to the boot partition via the first interface and a high-speed interface controller that provides host access to the user partition via the second interface.
14 . The non-transitory computer-readable storage medium of claim 13 , wherein the serial interface controller and the high-speed interface controller are initialized at least partly in parallel further in response to power being applied to the memory subsystem.
15 . A system comprising:
a plurality of memory devices; and
a processing device, operatively coupled with the plurality of memory devices, to:
responsive to power applied to a memory subsystem controller, transfer a primary boot loader from a memory device to a host system through a Quad Serial Peripheral Interface (QSPI), wherein the memory subsystem includes a boot partition and a user partition and is coupled to the host system by the QSPI and a second, high-speed interface, the QSPI providing the host system access to the boot partition and the high-speed interface providing the host system access to the user partition;
receive, by the memory subsystem controller, a request from the host system for a second stage boot loader; and
responsive to the request, transfer the second stage boot loader from the memory device to the host system through the high-speed interface.
16 . The system of claim 15 , wherein the second interface is one of a Peripheral Component Interconnect Express (PCIe), Serial Advanced Technology Attachment (SATA), and Unified Protocol (UniPro) interface.
17 . The system of claim 15 , wherein the processing device is further to:
set timing settings for accessing the boot partition via the QSPI.
18 . The system of claim 15 , wherein the primary boot loader is transferred before the second interface is initialized and available for transferring data from the memory device.
19 . The system of claim 15 , wherein the memory subsystem includes a serial interface controller that provides host access to the boot partition via the QSPI and a high-speed interface controller that provides host access to the user partition via the second interface.
20 . The system of claim 19 , wherein the serial interface controller and the high-speed interface controller are initialized at least partly in parallel further in response to power being applied to the memory subsystem.