READ OPERATIONS WITH OFFSET FOR SLOW CHARGE LOSS
Apparatuses and methods for performing read operations using an offset based upon slow charge loss characteristics are provided. One example apparatus can include a controller configured to apply a read voltage to a word line in the array of memory cells during a read operation on the word line, wherein the read voltage includes an offset associated with a slow charge loss characteristic of the word line.
1 . An apparatus, comprising:
an array of memory cells;
a controller coupled to the array of memory cells and the controller is configured to:
apply a read voltage to a word line in the array of memory cells during a read operation on the word line, wherein the read voltage includes an offset associated with a group of memory cells that includes the word line.
2 . The apparatus of claim 1 , wherein the group of memory cells that includes the word line are associated with a slow charge loss characteristic.
3 . The apparatus of claim 2 , wherein the offset is associated with the slow charge loss characteristic of the group of memory cells that includes the word line and is based upon a read level of the read voltage.
4 . The apparatus of claim 2 , wherein the slow charge loss characteristic includes edge sum (ESUM) loss at end of life (EOL) for the group of memory cells that includes the word line.
5 . The apparatus of claim 2 , wherein the slow charge loss characteristic includes center shift at end of life (EOL) for the group of memory cells that includes the word line.
6 . The apparatus of claim 1 , wherein the offset associated with the group of memory cells that includes the word line is stored in a look up table (LUT) in the array of memory cells.
7 . The apparatus of claim 6 , wherein the LUT includes offset values for each of a number of word lines in the array of memory cells.
8 . The apparatus of claim 6 , wherein the LUT includes offset values for each read level of a number read levels used during the read operation.
9 . The apparatus of claim 6 , wherein the LUT is stored in the controller.
10 . The apparatus of claim 1 , wherein the offset is included in the read voltage when executing a read command associated with the read operation.
11 . The apparatus of claim 1 , wherein the offset is associated with the read voltage in response to executing a command to apply the offset to the read voltage.
12 . The apparatus of claim 1 , wherein the offset is included in the read voltage during an error recovery step (ERS) operation.
13 . The apparatus of claim 1 , wherein the offset is included in the read voltage when executing the read operation before the read operation has triggered an error recover step (ERS).
14 . An apparatus, comprising:
an array of memory cells; and
a controller coupled to the array of memory cells and the controller is configured to:
apply a first read voltage to a first word line in the array of memory cells during a read operation on the word line, wherein the first read voltage is associated with a first read level of the read operation and the read voltage includes a first offset associated with a group of memory cells that includes the word line; and
apply a second read voltage to the first word line in the array of memory cells during the read operation on the word line, wherein the second read voltage is associated with a second read level of the read operation and the second read voltage includes a second offset associated with the group of memory cells that includes the word line.
15 . The apparatus of claim 14 , wherein the first offset and the second offset are associated with a slow charge loss characteristic of the word line associated with the group of memory cells that includes the word line.
16 . The apparatus of claim 14 , wherein the first read level and the second read level are associated with reading a lower page of the word line.
17 . The apparatus of claim 14 , wherein the first read level and the second read level are associated with reading an upper page of the word line.
18 . A method, comprising:
performing a read operation upon a word line in a memory array
wherein performing the read operation includes:
applying a first read voltage to a first word line in the array of memory cells during a read operation on the word line, wherein the first read voltage is associated with a first read level of the read operation and the read voltage includes a first offset associated with a group of memory cells that includes the word line; and
applying a second read voltage to the first word line in the array of memory cells during the read operation on the word line, wherein the second read voltage is associated with a second read level of the read operation and the second read voltage includes a second offset associated with the group of memory cells that includes the word line.
19 . The method of claim 18 , further including locating the first offset and the second offset in a look up table (LUT).
20 . The method of claim 18 , further including determining the first offset and the second offset based upon a slow charge loss characteristic of the word line associated with the group of memory cells that includes the word line.