SINGLE AND DUAL-EDGE TRIGGERED PHASE ERROR DETECTION
An example apparatus includes a sampling clock divider, a phase detector and a digital discriminator. The sampling clock divider generates a divided reference clock and a divided feedback clock by dividing a reference clock and a feedback clock, respectively using a sampling rate. The phase detector receives the divided reference clock and the divided feedback clock and sets status signal. The digital discriminator to receive samples of the status signal at the sampling rate and generate a locked status signal indicative of a locked status of a clock tracking circuit at least partially based on the samples of the status signal. Another apparatus may comprise a phase detector, a sampling logic circuit, a decimator, an interpolator, a multiplexer, and a digital discriminator.
1 . An apparatus, comprising:
a sampling clock divider to:
receive a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock; and
generate a divided reference clock and a divided feedback clock by dividing the reference clock and the feedback clock, respectively using a sampling rate;
a phase detector to receive the divided reference clock and the divided feedback clock and set a status signal that indicates a status of phase difference between the divided reference clock and the divided feedback clock; and
a digital discriminator to:
receive samples of the status signal at the sampling rate; and
generate a locked status signal indicative of a locked status of the clock tracking circuit at least partially based on the samples of the status signal.
2 . The apparatus of claim 1 , wherein clock rates of the divided reference clock and the divided feedback clock are greater than or less than those of the reference clock and the feedback clock based on the sampling rate.
3 . The apparatus of claim 1 , wherein the sampling rate is a value that represents a number of clock cycles per sampling interval or a number of samples per unit interval such that the sampling rate is pre-set by a user or logic circuit.
4 . The apparatus of claim 1 , wherein the status signal of the phase detector is sampled, and the samples of the status signal are decoded to determine the locked status.
5 . The apparatus of claim 1 , wherein the digital discriminator discriminates between steady-state phase error information and transitory phase error information in the status signal.
6 . The apparatus of claim 1 , wherein the digital discriminator keeps or passes the status signal that is indicative of steady-state phase error and blocks or discards the status signal that is indicative of transitory phase error.
7 . The apparatus of claim 1 , wherein the digital discriminator performs bit-wise comparison of a digital signal and predetermined patterns indicative of the locked status of the phase detector.
8 . The apparatus of claim 1 , wherein the digital discriminator accumulates a state of the status signal and detects when the accumulated state is above a predetermined threshold indicative of a steady-state phase error.
9 . The apparatus of claim 1 , wherein a status signal sample is a value of the status signal at specific intervals such as a discrete time or discrete value signal.
10 . The apparatus of claim 1 , wherein the sampling rate is set to ensure a set of samples obtained is representative of a phase detector’s state.
11 . An apparatus, comprising:
a phase detector to set a status signal that indicates a status of phase difference between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock;
a sampling logic circuit to generate samples of the status signal by sampling the status signal of the phase detector at a set sampling rate;
a decimator to decimate the status signal at a decimation rate to generate decimated samples;
an interpolator to interpolate the status signal at an interpolation rate to generate interpolated samples;
a multiplexer to select between the decimated samples and the interpolated samples at least partially based on a sampling rate selection; and
a digital discriminator to:
receive the selected samples; and
generate a locked status signal indicative of a locked status of the clock tracking circuit at least partially based on the selected samples.
12 . The apparatus of claim 11 , wherein the sampling logic circuit receives a sampling rate and determines whether to perform up-sampling based on the sampling rate to increase a number of samples based on interpolation.
13 . The apparatus of claim 11 , wherein the sampling logic circuit receives a sampling rate and determines whether to perform down-sampling based on the sampling rate to reduce a number of samples based on decimation.
14 . The apparatus of claim 11 , wherein the sampling logic circuit generates the decimation rate for the decimator or the interpolation rate for the interpolator and generates a selection signal to select an output of the decimator or the interpolator via the multiplexer as status signal samples are provided to the digital discriminator.
15 . The apparatus of claim 11 , wherein if the sampling logic circuit determines to perform up-sampling, then the sampling logic circuit determines a value for a target interpolation rate based on a sampling rate and sets an interpolation rate based on the determined value.
16 . The apparatus of claim 11 , wherein when up-sampling, the sampling logic circuit sets a decimation rate to a value indicative of no decimation.
17 . An apparatus, comprising:
a sampling clock divider to:
generate a divided reference clock and a divided feedback clock by dividing a reference clock and a feedback clock, respectively using a sampling rate;
a phase detector to receive the divided reference clock and the divided feedback clock and set a status signal; and
a digital discriminator to:
receive samples of the status signal at the sampling rate; and
generate a locked status signal indicative of a locked status of a clock tracking circuit at least partially based on the samples of the status signal.
18 . The apparatus of claim 17 , wherein clock rates of the divided reference clock and the divided feedback clock are greater than or less than those of the reference clock and the feedback clock based on the sampling rate that is being pre-set by a user or a logic circuit.
19 . The apparatus of claim 17 , wherein the status signal of the phase detector is sampled, and the samples of the status signal are decoded to determine the locked status.
20 . The apparatus of claim 17 , wherein the digital discriminator:
discriminates between steady-state phase error information and transitory phase error information in the status signal;
keeps or passes the status signal that is indicative of steady-state phase error and blocks or discards the status signal that is indicative of transitory phase error;
performs bit-wise comparison of a digital signal and predetermined patterns indicative of the locked status of the phase detector; and
accumulates a state of the status signal and detects when the accumulated state is above a predetermined threshold indicative of a steady-state phase error.