IP Library Patent Application 19630659
Patent Application
App. No. 19/630,659

CACHING LOOKUP TABLES FOR BLOCK FAMILY ERROR AVOIDANCE

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Quick Facts
Patent No.
US None
App. No.
19/630,659
Filed
Mar 27, 2026
Art Unit
OPAP
USPC
714/47.1
Abstract

In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.

Claims (55)

1 . A memory device, comprising:

one or more components configured to:

receive a read command for host data associated with a first memory location, wherein the host data is associated with a block family and the first memory location stores a subset of one or more block family error avoidance (BFEA) tables that are stored at a second memory location;

determine a modified threshold voltage by applying a threshold voltage offset to a base read level voltage associated with the host data, wherein the threshold voltage offset is determined based on the subset of the one or more BFEA tables; and

read, using the modified threshold voltage, the host data from the first memory location.

2 . The memory device of claim 1 , wherein the one or more components are further configured to:

associate a block family identifier with the threshold voltage offset, wherein the threshold voltage offset is further determined based on the block family.

3 . The memory device of claim 1 , wherein the one or more components are further configured to:

receive an indication that threshold voltage offset information associated with the block family has been updated; and

synchronize the subset of the one or more BFEA lookup tables with the threshold voltage offset information based on the indication.

4 . The memory device of claim 3 , wherein the one or more components are further configured to:

receive another read command for host data;

determine, based on the block family and the subset of the one or more BFEA tables stored in the first memory location, another threshold voltage offset associated with the host data, wherein the other threshold voltage offset is different than the threshold voltage offset;

compute another modified threshold voltage by applying the other threshold voltage offset to the base read level voltage associated with the host data; and

read, using the other modified threshold voltage, the host data from the first memory location.

5 . The memory device of claim 1 , wherein the block family includes a plurality of blocks that are associated with at least one of a time window during which the host data was written to the first memory location or a temperature window at which the host data was written to the first memory location.

6 . The memory device of claim 1 , wherein the one or more components are further configured to:

determine, based on a period of time elapsing, that threshold voltage offset information associated with the block family should be updated; and

update the threshold voltage offset information by updating the one or more BFEA lookup tables stored at the second memory location.

7 . The memory device of claim 1 ,

wherein the one or more BFEA lookup tables include at least a block partition table and a block family table, and

wherein the subset of the one or more BFEA tables stored in the first memory location includes a first subset of the block partition table and a second subset of the block family table.

8 . A memory device, comprising:

memory including at least a first memory location and a second memory location; and

a plurality of controllers operatively coupled to the memory and including at least a low-level controller associated with the first memory location and a high-level controller associated with the second memory location, the plurality of controllers configured to:

receive a write command associated with host data;

write the host data to the first memory location, wherein the host data is associated with a block family and the first memory location stores a subset of one or more block family error avoidance (BFEA) tables that are stored at the second memory location; and

read the host data from the first memory location using a modified threshold voltage that is obtained based on applying a threshold voltage offset to a base read level voltage associated with the host data, wherein the threshold voltage offset is determined based on the subset of the one or more BFEA tables.

9 . The memory device of claim 8 , wherein the plurality of controllers are further configured to:

associate the host data with the block family based on at least one of a time window during which the host data was written to the first memory location or a temperature window at which the host data was written to the first memory location.

10 . The memory device of claim 8 , wherein the one or more BFEA lookup tables are associated with multiple block families.

11 . The memory device of claim 8 , wherein the plurality of controllers are further configured to:

associate a block family identifier with the threshold voltage offset, wherein the threshold voltage offset is further determined based on the block family.

12 . The memory device of claim 8 , wherein the plurality of controllers are further configured to:

receive a read command associated with the host data.

13 . The memory device of claim 12 , wherein the plurality of controllers are further configured to:

receive an indication that threshold voltage offset information associated with the block family has been updated; and

synchronize the subset of the one or more BFEA lookup tables with the threshold voltage offset information associated with the block family based on the indication.

14 . The memory device of claim 13 , wherein the plurality of controllers are further configured to:

receive another read command associated with host data;

determine another threshold voltage offset based on the block family and the subset of the one or more BFEA tables stored in the first memory location, wherein the other threshold voltage offset is different than the threshold voltage offset;

compute another modified threshold voltage by applying the other threshold voltage offset to the base read level voltage associated with the host data; and

read, using the other modified threshold voltage, the host data from the first memory location.

15 . The memory device of claim 8 , wherein the block family includes a plurality of blocks that are associated with the at least one of a time window during which the host data was written to the first memory location or a temperature window at which the host data was written to the first memory location.

16 . The memory device of claim 8 , wherein the plurality of controllers are further configured to:

determine, based on a period of time elapsing, that threshold voltage offset information associated with the block family should be updated; and

update the threshold voltage offset information by updating the one or more BFEA lookup tables stored at the second memory location.

17 . The memory device of claim 8 , wherein the one or more BFEA lookup tables include at least a block partition table and a block family table, and wherein the subset of the one or more BFEA tables cached in the first memory location includes a first subset of the block partition table and a second subset of the block family table.

18 . A method, comprising:

receiving, by one or more controllers of a memory device, a write command associated with host data;

writing, by the one or more controllers of the memory device, the host data to a first memory location, wherein the host data is associated with a block family and the first memory location stores a subset of one or more block family error avoidance (BFEA) tables that are stored at a second memory location; and

reading, by the one or more controllers of the memory device, the host data from the first memory location using a modified threshold voltage that is obtained based on applying a threshold voltage offset to a base read level voltage associated with the host data, wherein the threshold voltage offset is determined based on the subset of the one or more BFEA tables.

19 . The method of claim 18 , further comprising:

associating the host data with the block family based on at least one of a time window during which the host data was written to the first memory location or a temperature window at which the host data was written to the first memory location.

20 . The method of claim 18 , wherein the one or more BFEA lookup tables are associated with multiple block families.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2026
From: BUKHARI, SHAKEEL ISAMOHIUDDIN; ISH, MARK
To: MICRON TECHNOLOGY, INC.
Reel/Frame 074220/0061 →