MEMORY DEVICES AND MICROELECTRONIC DEVICES
A microelectronic device includes a memory array structure and a control circuitry structure vertically overlying and bonded to the memory array structure. The memory array structure includes array regions respectively including memory cells, digit lines, and word lines within horizontal areas thereof. The control circuitry structure includes control circuitry regions, sense amplifier (SA) sections including SA circuitry, and sub-word line driver (SWD) sections including SWD circuitry. The control circuitry regions horizontally overlap the array regions of the memory array structure. The SA sections respectively horizontally overlap each of two of the control circuitry regions horizontally neighboring one another in a first direction. The SWD sections are respectively interposed between two other of the control circuitry regions horizontally neighboring one another in a second direction orthogonal to the first direction. Additional microelectronic devices, memory devices, and electronic systems are also described.
1 . A memory device, comprising:
a memory array structure comprising volatile memory cells coupled to digit lines and word lines; and
a control circuitry structure vertically overlying the memory array structure, the control circuitry structure comprising:
control circuitry regions;
sense amplifier sections, individual ones of the sense amplifier sections horizontally extending across a boundary between two of the control circuitry regions neighboring one another in a first direction;
column decoder sections within the control circuitry regions and horizontally neighboring the sense amplifier sections;
sub-word line driver sections between two of the control circuitry regions neighboring one another in a second direction perpendicular to the first direction; and
mini-gap sections respectively horizontally between neighboring ones of the sense amplifier sections and between neighboring ones of the sub-word line driver sections, the mini-gap sections comprising conductive routing structures.
2 . The memory device of claim 1 , wherein the control circuitry structure further comprises digit line contact regions horizontally overlapping digit line exit regions of the memory array structure, the digit line contact regions within horizontal areas of the sense amplifier sections.
3 . The memory device of claim 2 , wherein the digit line contact regions of the control circuitry structure comprise read/write gap areas of sense amplifier devices of the sense amplifier sections.
4 . The memory device of claim 2 , wherein the control circuitry structure further comprises word line contact regions horizontally overlapping word line exit regions of the memory array structure, the word line contact regions within horizontal areas of the sub-word line driver sections.
5 . The memory device of claim 1 , wherein the sense amplifier sections comprise sense amplifier devices, individual ones of the sense amplifier devices comprising:
a read/write gap area;
an N-type sense amplifier area neighboring the read/write gap area;
a voltage transfer characteristic area neighboring the N-type sense amplifier area;
a P-type sense amplifier area neighboring the voltage transfer characteristic area;
an additional voltage transfer characteristic area neighboring the P-type sense amplifier area;
an additional N-type sense amplifier area neighboring the additional voltage transfer characteristic area; and
a column select area neighboring the additional N-type sense amplifier area.
6 . The memory device of claim 5 , wherein, for a pair of the sense amplifier devices within an individual one of the sense amplifier sections, the read/write gap area of a first sense amplifier device of the pair is directly horizontally adjacent to the read/write gap area of a second sense amplifier device of the pair.
7 . The memory device of claim 1 , wherein the conductive routing structures of the mini-gap sections comprise conductive routing structures at different vertical elevations than one another.
8 . The memory device of claim 1 , wherein individual ones of the control circuitry regions comprise two of the column decoder sections within a horizontal area thereof.
9 . The memory device of claim 1 , wherein the volatile memory cells comprise dynamic random access memory cells.
10 . A microelectronic device, comprising:
a memory array structure comprising volatile memory cells coupled to digit lines and word lines; and
a control circuitry structure overlying and attached to the memory array structure through dielectric-to-dielectric bonds, the control circuitry structure comprising:
sense amplifier devices individually comprising N-type sense amplifier areas, voltage transfer characteristic areas, and P-type sense amplifier areas;
column decoders horizontally neighboring the sense amplifier devices;
sub-word line driver devices; and
routing sections horizontally interposed between neighboring pairs of the sense amplifier devices and between neighboring pairs of the sub-word line driver devices, the routing sections comprising conductive routing structures coupled to the sense amplifier devices and the sub-word line driver devices.
11 . The microelectronic device of claim 10 , wherein the sense amplifier devices further individually comprise:
a read/write gap area;
an additional N-type sense amplifier area neighboring an additional voltage transfer characteristic area; and
a column select area neighboring the additional N-type sense amplifier area.
12 . The microelectronic device of claim 11 , wherein, for a pair of the sense amplifier devices, the read/write gap area of a first sense amplifier device of the pair is directly horizontally adjacent to the read/write gap area of a second sense amplifier device of the pair.
13 . The microelectronic device of claim 12 , wherein horizontally adjacent read/write gap areas of the pair of the sense amplifier devices at least partially define a digit line contact region of the control circuitry structure.
14 . The microelectronic device of claim 10 , wherein the control circuitry structure further comprises control circuitry regions, individual ones of the sense amplifier devices horizontally overlapping and partially defining a respective one of the control circuitry regions.
15 . The microelectronic device of claim 14 , wherein the sub-word line driver devices are horizontally interposed between neighboring ones of the control circuitry regions, the sub-word line driver devices substantially confined outside of horizontal areas of the control circuitry regions.
16 . The microelectronic device of claim 14 , further comprising column decoder sections within the control circuitry regions and horizontally neighboring the sense amplifier devices.
17 . The microelectronic device of claim 10 , wherein the conductive routing structures of the routing sections comprise conductive routing structures at different vertical positions than one another.
18 . The microelectronic device of claim 10 , wherein the volatile memory cells comprise dynamic random access memory cells.
19 . A memory device, comprising:
a memory array structure comprising:
array regions comprising volatile memory cells coupled to digit lines and word lines;
digit line exit regions horizontally alternating with the array regions in a first direction; and
word line exit regions horizontally alternating with the array regions in a second direction perpendicular to the first direction; and
a control circuitry structure overlying the memory array structure, the control circuitry structure comprising:
control circuitry regions horizontally overlapping the array regions of the memory array structure;
sense amplifier sections, respective ones of the sense amplifier sections horizontally extending across a boundary between two of the control circuitry regions neighboring one another in the first direction, the sense amplifier sections comprising sense amplifier devices;
digit line contact regions within horizontal areas of the sense amplifier sections and horizontally overlapping the digit line exit regions, the digit line contact regions at least partially defined by read/write gap areas of the sense amplifier devices;
sub-word line driver sections between two of the control circuitry regions neighboring one another in the second direction; and
word line contact regions within horizontal areas of the sub-word line driver sections and horizontally overlapping the word line exit regions.
20 . The memory device of claim 19 , further comprising:
column decoder sections within the control circuitry regions and horizontally neighboring the sense amplifier sections; and
mini-gap sections respectively horizontally between neighboring ones of the sense amplifier sections and between neighboring ones of the sub-word line driver sections.