COMMAND BUS TRAINING FOR MEMORY SYSTEM
Various aspects of the present disclosure generally relate to memory devices. In some aspects, a volatile memory device may receive, from a host device, a clock (CK) signal. The memory device may receive, from the host device, a command address (CA) signal associated with a continuous long burst pseudo-random binary sequence (PRBS) pattern. The memory device may perform a command bus training (CBT) based at least in part on the CA signal in relation to the CK signal. The memory device may provide, to the host device, pass or fail results associated with the CBT. Numerous other aspects are described.
1 . A host device, comprising: one or more controllers configured to: transmit, to a volatile memory device, a clock (CK) signal; transmit, to the volatile memory device, a command address (CA) signal associated with a continuous long burst pseudo-random binary sequence (PRBS) pattern; and receive, from the volatile memory device, pass or fail results associated with a command bus training (CBT), wherein a pass or fail result associated with a first data in or out (DQ) bus corresponds to the CA signal latched with a rising edge of the CK signal and a pass or fail result associated with a second DQ bus corresponds to the CA signal latched with a falling edge of the CK signal.
2 . The host device of claim 1 , wherein a length of the continuous long burst PRBS pattern is based at least in part on a range of one thousand to four thousand bits, wherein the CBT is based at least in part on the CA signal in relation to the CK signal, and wherein the pass or fail results are received from the volatile memory device via the first DQ bus and the second DQ bus.
3 . The host device of claim 1 , wherein the CBT is associated with an adjustment of a per-bit skew and a duty cycle distortion.
4 . The host device of claim 1 , wherein the one or more controllers are further configured to transmit, to the volatile memory device, a chip select (CS) signal, wherein the CA signal is transmitted when the CS signal is associated with a high value.
5 . The host device of claim 1 , wherein the volatile memory device includes a linear-feedback shift register (LFSR), and the LFSR is associated with a same predefined seed sequence as compared to an LFSR associated with the host device.
6 . The host device of claim 1 , wherein the CBT provides training for one or more of: inter-symbol interference, cross-talk, or voltage noise.
7 . The host device of claim 1 , wherein the one or more controllers are further configured to: transmit an entry or exit function of the CBT via a third DQ signal.
8 . A method, comprising: transmitting, to a volatile memory device, a clock (CK) signal; transmitting, to the volatile memory device, a command address (CA) signal associated with a continuous long burst pseudo-random binary sequence (PRBS) pattern; and receiving, from the volatile memory device, pass or fail results associated with a command bus training (CBT), wherein a pass or fail result associated with a first data in or out (DQ) bus corresponds to the CA signal latched with a rising edge of the CK signal and a pass or fail result associated with a second DQ bus corresponds to the CA signal latched with a falling edge of the CK signal.
9 . The method of claim 8 , wherein a length of the continuous long burst PRBS pattern is based at least in part on a range of one thousand to four thousand bits, wherein the CBT is based at least in part on the CA signal in relation to the CK signal, and wherein the pass or fail results are received from the volatile memory device via the first DQ bus and the second DQ bus.
10 . The method of claim 8 , wherein the CBT is associated with an adjustment of a per-bit skew and a duty cycle distortion.
11 . The method of claim 8 , further comprising: transmitting, to the volatile memory device, a chip select (CS) signal, wherein the CA signal is received when the CS signal is associated with a high value.
12 . The method of claim 8 , wherein the volatile memory device includes a linear-feedback shift register (LFSR), and the LFSR is associated with a same predefined seed sequence as compared to an LFSR associated with a host device.
13 . The method of claim 8 , wherein the CBT provides training for one or more of: inter-symbol interference, cross-talk, or voltage noise.
14 . The method of claim 8 , further comprising: transmitting, to the volatile memory device, one or more additional CA signals; and receiving, from the volatile memory device and via one or more additional DQ buses, additional pass or fail results associated with the CBT.
15 . A system, comprising: a host device configured to transmit a clock (CK) signal; and transmit a command address (CA) signal associated with a continuous long burst pseudo-random binary sequence (PRBS) pattern; and receive pass or fail results associated with a command bus training (CBT), wherein a pass or fail result associated with a first data in or out (DQ) bus corresponds to the CA signal latched with a rising edge of the CK signal and a pass or fail result associated with a second DQ bus corresponds to the CA signal latched with a falling edge of the CK signal.
16 . The system of claim 15 , wherein a length of the continuous long burst PRBS pattern is based at least in part on a range of one thousand to four thousand bits, wherein the CBT is based at least in part on the CA signal in relation to the CK signal, and wherein the pass or fail results are received via the first DQ bus and the second DQ bus.
17 . The system of claim 15 , wherein the CBT is associated with an adjustment of a per-bit skew and a duty cycle distortion.
18 . The system of claim 15 , wherein the host device is further configured to: transmit a chip select (CS) signal, wherein the CA signal is received when the CS signal is associated with a high value.
19 . The system of claim 15 , wherein the host device is further configured to: transmit an entry or exit function of the CBT via a third DQ signal.
20 . The system of claim 15 , wherein the CBT provides training for one or more of: inter-symbol interference, cross-talk, or voltage noise.