METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A VICTIM CACHE

1 . A circuit comprising:

a first latch having an output;

a second latch an input and an output, the input coupled to the output of the first latch;

a third latch having an input and an output, the input coupled to the output of the second latch;

a fourth latch having an input and an output, the input coupled to the output of the third latch; and

at least one merge circuit having an input, a first output, a second output, and a third output, the input coupled to the output of the fourth latch, the first output coupled to the input of the fourth latch, the second output coupled to the input of the third latch, and the third output coupled to the input of the second latch.

2 . The circuit of claim 1 , wherein the at least one merge circuit comprises:

a first merge circuit having an input, a first output, and a second output, the input being the input of the at least one merge circuit and the second output being the first output of the at least one merge circuit;

a second merge circuit having an input, a first output, and a second output, the input coupled to the first output of the first merge circuit, and the second output being the second output of the at least one merge circuit; and

a third merge circuit having an input and an output, the input coupled to the first output of the second merge circuit and the output being the third output of the at least one merge circuit.

3 . The circuit of claim 1 , wherein the at least one merge circuit comprises:

comparators; and

switches coupled to the comparators.

4 . The circuit of claim 1 , wherein the output of the first latch is a first output, the circuit further comprising:

a random access memory (RAM) having an input and an output, the input coupled to a second output of the first latch;

a memory having an input and an output, the input coupled to the output of the RAM;

a fifth latch having an input and an output, the input coupled to the output of the memory; and

an error detection and correction circuit having an input coupled to the output of the fifth latch.

5 . The circuit of claim 4 , further comprising:

error correcting code (ECC) logic having an input and an output, the input coupled to the output of the fourth latch; and

an arbitration circuit having a first input, a second input, and an output, the first input coupled to the first output of the first latch, the second input coupled to the output of the ECC logic, and the output coupled to the input of the memory.

6 . The circuit of claim 5 , further comprising:

a first multiplexer having a first input, a second input, a third input, a fourth input, and an output, the first input coupled to the output of the second latch, the second input coupled to the output of the third latch, the third input coupled to the at least one merge circuit, the fourth input coupled to the output of the ECC logic;

a sixth latch having an input and an output, the input coupled to the output of the first multiplexer;

a second multiplexer having a first input, a second input, and an output, the first input coupled to the output of the sixth latch and the second input coupled to the output of the error detection and correction circuit; and

a seventh latch having an input coupled to the output of the second multiplexer.

7 . The circuit of claim 4 , further comprising:

an arithmetic unit having a first input, a second input, a third input, and an output, the first input coupled to the output of the third latch, the second input coupled to the first output of the at least one merge circuit, and the third input coupled to the output of the error detection and correction circuit;

an atomic compare circuit having a first input, a second input, a third input, and an output, the first input coupled to the output of the third latch, the second input coupled to the first output of the at least one merge circuit, and the third input coupled to the output of the error detection and correction circuit; and

a read-modify-write merge circuit having a first input, a second input, a third input, and an output, the first input coupled to the output of the third latch, the second input coupled to the first output of the at least one merge circuit, and the third input coupled to the output of the error detection and correction circuit; and

a multiplexer having a first input, a second input, a third input, and an output, the first input coupled to the output of the arithmetic unit, the second input coupled to the output of the atomic compare circuit, the third input coupled to the output of the read-modify-write merge circuit, and the output coupled to the input of the fourth latch.

8 . A method comprising:

receiving first data from a first storage;

receiving second data from a second storage;

merging the first data and the second data to produce third data; and

storing the third data in the second storage.

9 . The method of claim 8 , further comprising receiving a memory operation that indicates an address, and wherein the second data is associated with the address.

10 . The method of claim 8 , further comprising:

producing error correcting code (ECC) syndrome bits based on the third data; and

storing the ECC syndrome bits in the second storage.

11 . The method of claim 8 , wherein the first storage is main cache storage and the second storage is victim cache storage.

12 . The method of claim 8 , further comprising receiving a write request, wherein receiving the second data, merging the first data and the second data, and storing the third data are performed based on the write request.

13 . The method of claim 12 , further comprising, based on the write request, producing a read request associated with the first data.

14 . A system comprising:

a central processing unit (CPU) configured to produce a memory operation;

a level one (L1) cache coupled to the CPU, the L1 cache comprising:

a first storage;

a second storage; and

a storage queue configured to:

receive the memory operation;

receive first data from the first storage;

receive second data from the second storage based on the memory operation;

merge the first data and the second data to produce third data; and

store the third data in the second storage; and

a level two (L2) cache coupled to the L1 cache, the L2 cache configured to receive the third data and store the third data.

15 . The system of claim 14 , wherein the first storage is main cache storage and the second storage is victim cache storage.

16 . The system of claim 14 , wherein the memory operation indicates an address, and the second data is associated with the address.

17 . The system of claim 14 , wherein the storage queue comprises a merge circuit configured to merge the first data and the second data.

18 . The system of claim 14 , wherein the storage queue comprises an error correcting code (ECC) circuit configured to produce ECC syndrome bits based on the third data, wherein the storage queue is further configured to store the ECC syndrome bits in the second storage.

19 . The system of claim 14 , wherein the storage queue comprises:

a first latch having an output;

a second latch an input and an output, the input coupled to the output of the first latch;

a third latch having an input and an output, the input coupled to the output of the second latch;

a fourth latch having an input and an output, the input coupled to the output of the third latch; and

at least one merge circuit having an input, a first output, a second output, and a third output, the input coupled to the output of the fourth latch, the first output coupled to the input of the fourth latch, the second output coupled to the input of the third latch, and the third output coupled to the input of the second latch.

20 . The system of claim 19 , wherein the at least one merge circuit comprises:

a first merge circuit having an input, a first output, and a second output, the input being the input of the at least one merge circuit and the second output being the first output of the at least one merge circuit;

a second merge circuit having an input, a first output, and a second output, the input coupled to the first output of the first merge circuit, and the second output being the second output of the at least one merge circuit; and

a third merge circuit having an input and an output, the input coupled to the first output of the second merge circuit and the output being the third output of the at least one merge circuit.