DETECTING DATA BUS DRIVE FAULTS
Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid.
1 . A memory system, comprising:
a first circuit coupled with one or more first pins and configured to bias the one or more first pins to a first voltage level via termination to a first voltage source; and
a second circuit coupled with a second pin and configured to bias the second pin to a second voltage level via termination to a second voltage source, the second voltage level being different than the first voltage level.
2 . The memory system of claim 1 , wherein:
the first circuit is configured to bias the one or more first pins to the first voltage level in response to the one or more first pins being in an idle state, and
the second circuit is configured to bias the second pin to the second voltage level in response to the second pin being in the idle state.
3 . The memory system of claim 1 , wherein:
the one or more first pins comprise one or more data pins, and
the second pin comprises an error correction information pin.
4 . The memory system of claim 1 , wherein:
the first voltage source is configured to supply the first voltage level,
the second voltage source is configured to supply the second voltage level, and
the first voltage level is lower than the second voltage level.
5 . The memory system of claim 1 , wherein:
the first circuit comprises a first impedance positioned between the one or more first pins and the first voltage source, and
the second circuit comprises a second impedance positioned between the second pin and the second voltage source.
6 . The memory system of claim 1 , further comprising:
a driver coupled with the second pin and configured to apply one or more voltages to the second pin, wherein the one or more voltages applied by the driver are configured to override the second voltage level applied by the second circuit.
7 . The memory system of claim 1 , further comprising:
one or more first lines coupled with the one or more first pins, wherein the first circuit is coupled with the one or more first lines; and
a second line coupled with the second pin, wherein the second circuit is coupled with the second line.
8 . The memory system of claim 1 , further comprising:
a bus coupled with the one or more first pins and the second pin, wherein the bus is configured to receive one or more commands from a host system.
9 . A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
bias one or more first pins to a first voltage;
output, via the one or more first pins, a first signal based at least in part on biasing the one or more first pins to the first voltage;
bias a second pin to a second voltage, wherein the second voltage is different than the first voltage; and
output, via the second pin, a second signal based at least in part on biasing the second pin to the second voltage.
10 . The memory system of claim 9 , wherein a validity of the first signal is indicated based at least in part on the second signal.
11 . The memory system of claim 9 , wherein:
the one or more first pins are biased to the first voltage in response to the one or more first pins being in an idle state, and
the second pin is biased to the second voltage in response to the second pin being in the idle state.
12 . The memory system of claim 9 , wherein:
the one or more first pins comprise one or more data pins, and
the second pin comprises an error correction information pin.
13 . The memory system of claim 9 , wherein the processing circuitry is further configured to cause the memory system to:
receive a read command;
retrieve a set of data in response to the read command; and
apply, based at least in part on the set of data, a set of voltages to the one or more first pins during a first duration of a read operation triggered by the read command.
14 . The memory system of claim 13 , wherein the processing circuitry is further configured to cause the memory system to:
generate an error correction code for the set of data based at least in part on retrieving the set of data; and
apply, based at least in part on the error correction code, a second set of voltages to the second pin during a second duration of the read operation.
15 . The memory system of claim 14 , wherein the second set of voltages applied to the second pin overrides the second voltage applied to the second pin.
16 . The memory system of claim 9 , wherein the second signal is indicative of a validity of a set of data represented by the first voltage during a first duration of a read operation.
17 . The memory system of claim 9 , wherein the first signal and the second signal are configured to indicate an absence of a valid read operation based at least in part on the first signal having the first voltage during a first duration of a read operation and the second signal having the second voltage during a second duration of the read operation.
18 . The memory system of claim 9 , wherein:
the one or more first pins are biased to the first voltage via a first circuit that couples the one or more first pins with a first voltage source, and
the second pin is biased to the second voltage via a second circuit that couples the second pin with a second voltage source.
19 . A method, comprising:
biasing one or more first pins to a first voltage;
outputting, via the one or more first pins, a first signal based at least in part on biasing the one or more first pins to the first voltage;
biasing a second pin to a second voltage, wherein the second voltage is different than the first voltage; and
outputting, via the second pin, a second signal based at least in part on biasing the second pin to the second voltage.
20 . The method of claim 19 , wherein a validity of the first signal is indicated based at least in part on the second signal.