3D CHIP PACKAGE BASED ON THROUGH-SILICON-VIA INTERCONNECTION ELEVATOR
A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the top surface of each of the plurality of first through vias, wherein the second interconnection scheme comprises a plurality of second metal contacts at a top surface of the chip package.
1 . A chip package comprising:
a semiconductor chip comprising:
a first silicon substrate,
a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first insulating dielectric layer over the first silicon substrate, a first interconnection metal layer on a top surface of the first insulating dielectric layer, a second interconnection metal layer over the first interconnection metal layer, a second insulating dielectric layer between the first and second interconnection metal layers and a third insulating dielectric layer on the second interconnection metal layer, wherein the first insulating dielectric layer comprises silicon and oxygen, and wherein the first interconnection metal layer comprises a first copper layer over the top surface of the first insulating dielectric layer and a first adhesion metal layer at a first bottom and first sidewall of the first copper layer and between the first bottom of the first copper layer and the top surface of the first insulating dielectric layer, wherein the first sidewall of the first copper layer is vertically over the top surface of the first insulating dielectric layer,
a first metal contact at a top of the semiconductor chip, wherein the first metal contact extends horizontally on a top surface of the third insulating dielectric layer and downwards into an opening in the third insulating dielectric layer and is in contact with the second interconnection metal layer, wherein the first metal contact comprises a second copper layer at the top of the semiconductor chip, and
a first electronic component at a same horizontal level as the semiconductor chip, wherein the first electronic component comprises:
a second silicon substrate,
a first decoupling capacitor comprising a first electrode having a portion vertically in the second silicon substrate, and
a second metal contact at a top of the first electronic component and coupling to the first decoupling capacitor;
a dummy chip at the same horizontal level as the semiconductor chip and the first electronic component;
a metal interconnect extending vertically for vertical interconnection and at the same horizontal level as the semiconductor chip, the first electronic component and the dummy chip;
a first polymer layer at the same horizontal level as the semiconductor chip, the first electronic component, the dummy chip and the metal interconnect, wherein the first polymer layer contacts a sidewall of each of the semiconductor chip, the first electronic component and the dummy chip and has a bottom surface coplanar with a bottom surface of each of the semiconductor chip, the first electronic component and the dummy chip;
a second interconnection scheme over the semiconductor chip, the first electronic component, the dummy chip, the metal interconnect and the first polymer layer and coupling to the metal interconnect, wherein the second interconnection scheme comprises:
a fourth insulating dielectric layer over the semiconductor chip, the first electronic component, the dummy chip and the first polymer layer,
a third interconnection metal layer over the fourth insulating dielectric layer, and
a fifth insulating dielectric layer over the third interconnection metal layer and the fourth insulating dielectric layer, wherein an opening in the fifth insulating dielectric layer is over the third interconnection metal layer; and
a first metal bump extending horizontally on a top surface of the fifth insulating dielectric layer and downwards into the opening in the fifth insulating dielectric layer and in contact with the third interconnection metal layer, wherein the first metal bump comprises a third copper layer.
2 . The chip package of claim 1 , wherein the first decoupling capacitor further comprises a second electrode having a portion vertically in the second silicon substrate and a dielectric layer having a portion between the portion of the first electrode and the portion of the second electrode and in contact with the portion of the first electrode and the portion of the second electrode.
3 . The chip package of claim 2 , wherein the dielectric layer of the first decoupling capacitor comprises an oxide material.
4 . The chip package of claim 1 , wherein the portion of the first electrode has a depth between 5 and 30 micrometers in the second silicon substrate.
5 . The chip package of claim 1 , wherein the first electrode of the first decoupling capacitor comprises titanium.
6 . The chip package of claim 1 , wherein the first electrode of the first decoupling capacitor couples to a voltage (Vss) of ground reference.
7 . The chip package of claim 1 further comprising a second electronic component at the same horizontal level as the semiconductor chip, the first electronic component, the dummy chip, the metal interconnect and the first polymer layer and under the second interconnection scheme, wherein the second electronic component comprises a third silicon substrate and a second decoupling capacitor comprising a second electrode having a portion vertically in the third silicon substrate.
8 . The chip package of claim 1 , wherein a distance between the semiconductor chip and an edge of the chip package is greater than 1,500 micrometers and the dummy chip is between the semiconductor chip and the edge of the chip package.
9 . The chip package of claim 1 , wherein the dummy chip does not provide any electrical function.
10 . The chip package of claim 1 , wherein the dummy chip is between the semiconductor chip and an edge of the chip package and the first polymer layer has a first portion between the dummy chip and the edge of the chip package and contacting a first sidewall of the dummy chip and a second portion between the dummy chip and the semiconductor chip and contacting a second sidewall of the dummy chip.
11 . The chip package of claim 1 , wherein the first interconnection scheme further comprises a sixth insulating dielectric layer on the top surface of the first insulating dielectric layer, wherein the sixth insulating dielectric layer comprises silicon and oxygen, wherein the first interconnection metal layer is further in an opening in the sixth insulating dielectric layer and the first adhesion metal layer is further between the first sidewall of the first copper layer and the sixth insulating dielectric layer.
12 . The chip package of claim 1 , wherein the first interconnection metal layer further extends downwards into an opening in the first insulating dielectric layer, wherein the first copper layer further extends downwards into the opening in the first insulating dielectric layer, wherein the first copper layer has a second sidewall and second bottom in the opening in the first insulating dielectric layer, wherein the first adhesion metal layer is further at the second sidewall of the first copper layer, between the second sidewall of the first copper layer and the first insulating dielectric layer and at the second bottom of the first copper layer.
13 . The chip package of claim 1 , wherein the second interconnection metal layer extends horizontally on a top surface of the second insulating dielectric layer and downwards into an opening in the second insulating dielectric layer, wherein the second interconnection metal layer comprises a bulk metal layer having a sidewall vertically over the top surface of the second insulating dielectric layer and a second adhesion metal layer at a bottom of the bulk metal layer and between the bulk metal layer and the top surface of the second insulating dielectric layer, wherein the second adhesion metal layer is not at the sidewall of the bulk metal layer.
14 . The chip package of claim 1 , wherein the second copper layer of the first metal contact has a sidewall vertically over the top surface of the third insulating dielectric layer, wherein the first metal contact further comprises a second adhesion metal layer at a bottom of the second copper layer and not at the sidewall of the second copper layer.
15 . The chip package of claim 1 , wherein the semiconductor chip further comprises a second polymer layer at the top of the semiconductor chip and in contact with a sidewall of the first metal contact, wherein the second polymer layer has a top surface coplanar with a top surface of the first polymer layer.
16 . The chip package of claim 1 , wherein the second metal contact comprises a fourth copper layer at the top of the first electronic component.
17 . The chip package of claim 16 , wherein the fourth copper layer has a top surface coplanar with a top surface of the second copper layer of the first metal contact at the top of the semiconductor chip.
18 . The chip package of claim 1 , wherein the first electronic component further comprises a second polymer layer at the top of the first electronic component and in contact with a sidewall of the second metal contact, wherein the second polymer layer has a top surface coplanar with a top surface of the first polymer layer.
19 . The chip package of claim 1 , wherein the metal interconnect comprises a fourth copper layer extending in a vertical direction and has a vertical dimension between 30 and 200 micrometers.
20 . The chip package of claim 1 , wherein the fourth insulating dielectric layer of the second interconnection scheme comprises a second polymer layer.
21 . The chip package of claim 1 , wherein the fourth insulating dielectric layer of the second interconnection scheme comprises polyimide.
22 . The chip package of claim 1 , wherein the second interconnection scheme further comprises:
a sixth insulating dielectric layer on a top surface of the first polymer layer and a top surface of each of the semiconductor chip, the first electronic component and the dummy chip, wherein a first opening in the sixth insulating dielectric layer is vertically over the first metal contact, a second opening in the sixth insulating dielectric layer is vertically over the second metal contact and a third opening in the sixth insulating dielectric layer is vertically over the metal interconnect; and
a fourth interconnection metal layer extending horizontally on a top surface of the sixth insulating dielectric layer and downwards into the first, second and third openings in the sixth insulating dielectric layer and in contact with a top surface of each of the first metal contact, the second metal contact and the metal interconnect, wherein the fourth insulating dielectric layer is over the sixth insulating dielectric layer and the fourth interconnection metal layer.
23 . The chip package of claim 1 , wherein the third interconnection metal layer extends horizontally on a top surface of the fourth insulating dielectric layer and downwards into an opening in the fourth insulating dielectric layer, wherein the third interconnection metal layer comprises a fourth copper layer having a sidewall vertically over the top surface of the fourth insulating dielectric layer and a second adhesion metal layer at a bottom of the fourth copper layer and between the fourth copper layer and the top surface of the fourth insulating dielectric layer, wherein the second adhesion metal layer is not at the sidewall of the fourth copper layer.
24 . The chip package of claim 1 , wherein the first metal bump further comprises a second adhesion metal layer at a bottom of the third copper layer, in contact with the third interconnection metal layer and the top surface of the fifth insulating dielectric layer and not at a sidewall of the third copper layer, wherein the sidewall of the third copper layer is vertically over the top surface of the fifth insulating dielectric layer.
25 . The chip package of claim 1 further comprising a third interconnection scheme under the semiconductor chip, the first electronic component, the dummy chip, the metal interconnect and the first polymer layer, wherein the third interconnection scheme comprises:
a sixth insulating dielectric layer under the semiconductor chip, the first electronic component, the dummy chip and the first polymer layer;
a fourth interconnection metal layer under the sixth insulating dielectric layer; and
a seventh insulating dielectric layer under the fourth interconnection metal layer and the sixth insulating dielectric layer and at a bottom of the chip package.
26 . The chip package of claim 25 , wherein the third interconnection scheme further comprises:
an eighth insulating dielectric layer under and in contact with the bottom surface of each of the semiconductor chip, the first electronic component, the dummy chip and the first polymer layer, wherein an opening in the eighth insulating dielectric layer is vertically under the metal interconnect; and
a fifth interconnection metal layer extending horizontally on a bottom surface of the eighth insulating dielectric layer and upwards into the opening in the eighth insulating dielectric layer and in contact with a bottom surface of the metal interconnect, wherein the sixth insulating dielectric layer is under the eighth insulating dielectric layer and the fifth interconnection metal layer.
27 . The chip package of claim 25 , wherein the fourth interconnection metal layer extends horizontally on a bottom surface of the sixth insulating dielectric layer and upwards into an opening in the sixth insulating dielectric layer, wherein the fourth interconnection metal layer comprises a fourth copper layer having a sidewall vertically under the bottom surface of the sixth insulating dielectric layer and a second adhesion metal layer at a top of the fourth copper layer and between the fourth copper layer and the bottom surface of the sixth insulating dielectric layer, wherein the second adhesion metal layer is not at the sidewall of the fourth copper layer.
28 . The chip package of claim 25 further comprising a third metal contact at a bottom of the chip package and at a bottom of the third interconnection scheme, wherein the third metal contact is configured for coupling to an external circuit of the chip package.
29 . The chip package of claim 1 , wherein the first polymer layer comprises a molding compound.
30 . The chip package of claim 1 , wherein the semiconductor chip comprises a semiconductor integrated-circuit (IC) chip, wherein the semiconductor integrated-circuit (IC) chip is a logic chip.