MEMORY DEVICES

1 . A volatile memory device, comprising:

a first die comprising:

an array region comprising memory cells individually comprising:

two transistor structures horizontally neighboring one another and individually comprising vertically spaced channel regions; and

a capacitor structure coupled to the two transistor structures; and

a peripheral region horizontally neighboring the array region and comprising sub word line driver (SWD) circuitry;

a second die bonded to the first die and comprising:

a base structure comprising semiconductive material;

sense amplifier (SA) transistors individually comprising:

conductively doped regions within the base structure;

a channel region of the base structure horizontally interposed between the conductively doped regions; and

a gate structure vertically neighboring the channel region; and

complementary metal oxide semiconductor (CMOS) transistors horizontally neighboring the SA transistors and individually comprising:

additional conductively doped regions within the base structure;

an additional channel region of the base structure horizontally interposed between the additional conductively doped regions; and

an additional gate structure vertically neighboring the additional channel region; and

conductive pad structures, the second die vertically interposed between the first die and the conductive pad structures.

2 . The volatile memory device of claim 1 , further comprising a gate dielectric material vertically interposed between the gate structure and the channel region of each of the SA transistors.

3 . The volatile memory device of claim 1 , further comprising an additional gate dielectric material vertically interposed between the additional gate structure and the additional channel region of each of the CMOS transistors.

4 . The volatile memory device of claim 1 , wherein:

the conductively doped regions of respective ones of the SA transistors comprise a source region and a drain region; and

the additional conductively doped regions of respective ones of the CMOS transistors comprise an additional source region and an additional drain region.

5 . The volatile memory device of claim 1 , further comprising word line structures surrounding the vertically spaced channel regions of the two transistor structures.

6 . The volatile memory device of claim 1 , wherein the capacitor structure vertically underlies the two transistor structures.

7 . The volatile memory device of claim 1 , wherein:

the SA transistors are within a horizontal area of the array region; and

the CMOS transistors are within a horizontal area of the peripheral region.

8 . The volatile memory device of claim 1 , further comprising routing structures vertically interposed between the second die and the conductive pad structures.

9 . A volatile memory device, comprising:

a first die comprising:

a stack structure comprising:

levels of insulative material; and

levels of semiconductive material vertically alternating with the levels of insulative material;

memory cells within the stack structure and individually comprising:

a first transistor structure including a channel region comprising a portion of the semiconductive material;

a second transistor structure horizontally neighboring the first transistor structure and including an additional channel region comprising an additional portion of the semiconductive material; and

a capacitor coupled to the first transistor structure and the second transistor structure;

digit line contact structures vertically extending through the stack structure and individually in electrical communication with the channel region and the additional channel region of respective ones of the memory cells;

digit line structures vertically over the digit line contact structures and individually comprising:

a first section horizontally extending in a first direction; and

second sections integral with the first section and horizontally extending in a second direction orthogonal to the first direction, individual ones of the second sections in contact with individual ones of the digit line contact structures;

decoupling capacitor structures horizontally offset from the memory cells and vertically overlapping the capacitor of respective ones of the memory cells; and

a conductive plate structure horizontally extending between horizontally neighboring columns of the decoupling capacitor structures; and

a second die bonded to the first die and comprising sense amplifier circuits vertically over the digit line structures.

10 . The volatile memory device of claim 9 , further comprising word line structures surrounding the channel region of the first transistor structure and the additional channel region of the second transistor structure.

11 . The volatile memory device of claim 10 , wherein the first section of each of the digit line structures vertically overlies the word line structures and horizontally extends in parallel with the word line structures.

12 . The volatile memory device of claim 9 , wherein the stack structure comprises greater than or equal to eight of the levels of semiconductive material.

13 . The volatile memory device of claim 9 , wherein:

the decoupling capacitor structures individually comprise a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode; and

the conductive plate structure comprises a same material as the first electrode.

14 . The volatile memory device of claim 9 , further comprising sub word line driver (SWD) circuitry horizontally neighboring the memory cells, the decoupling capacitor structures vertically overlapping the SWD circuitry.

15 . The volatile memory device of claim 9 , further comprising a conductive contact structure vertically extending to and in contact with the conductive plate structure.

16 . A dynamic random access memory (DRAM) device, comprising:

a first die comprising:

memory cells individually comprising:

a first transistor and a second transistor horizontally neighboring the first transistor, the first transistor and the second transistor individually comprising:

channel region; and

conductive word line structure vertically neighboring the channel region;

a capacitor comprising:

a first electrode coupled to the first transistor; and

a second electrode coupled to the second transistor; and

conductive routing structures vertically interposed between the capacitor and each of the first transistor and the second transistor; and

digit line structures coupled to the first transistor and the second transistor of the memory cells; and

a second die vertically overlying the first die and comprising sense amplifier circuitry operably connected to the digit line structures.

17 . The DRAM device of claim 16 , wherein the capacitor further comprises dielectric material between the first electrode and the second electrode.

18 . The DRAM device of claim 16 , further comprising digit line contact structures vertically interposed between the digit line structures and the memory cells, individual ones of the digit line contact structures in contact with individual ones of the digit line structures.

19 . The DRAM device of claim 16 , wherein the capacitor vertically underlies the first transistor and the second transistor.

20 . The DRAM device of claim 16 , wherein the second die further comprises complementary metal oxide semiconductor (CMOS) circuitry horizontally neighboring the sense amplifier circuitry.