IP Library › Granted Patent US 730,304
Granted Patent S1
US 730,304 · App. 29/500,867 · Granted May 26, 2015

Substrate for an electronic circuit

Inventors: Manabu Matsumoto (Yokosuka, JP); Isao Ozawa (Yokosuka, JP)
Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 730,304
App. No.
29/500,867
Granted
May 26, 2015
Kind
S1
Claims (1)

The ornamental design for a substrate for an electronic circuit, as shown and described.

Assignments (3)
CHANGE OF NAME Recorded Feb 7, 2020
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 051842/0627 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2018
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 045175/0632 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2014
From: MATSUMOTO, MANABU; OZAWA, ISAO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 033639/0755 →
Priority Claims (1)
JP 2014-010413 · May 15, 2014 · national