IP Library › Granted Patent US 787,457
Granted Patent S1
US 787,457 · App. 29/533,047 · Granted May 23, 2017

Substrate for an electronic circuit

Inventors: Manabu Matsumoto (Yokohama, JP); Yasumasa Toyoda (Yokohama, JP)
Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 787,457
App. No.
29/533,047
Granted
May 23, 2017
Kind
S1
Claims (1)

The ornamental design for a substrate for an electronic circuit, as shown and described.

Assignments (3)
CHANGE OF NAME Recorded Feb 7, 2020
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 051842/0627 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2018
From: KABUSHIKI KAISHA TOSHIBA
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA MEMORY CORPORATION
Reel/Frame 045103/0298 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2015
From: MATSUMOTO, MANABU; TOYODA, YASUMASA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 036077/0329 →
Priority Claims (1)
JP 2015-000435 · Jan 14, 2015 · national