Patent Application
Provisional
App. No. 60/620,966
· Confirmation No. 5406
Layout techniques for low parasitic capacitance in analog circuit application
Inventor:
Chun-Ying Chen
Provisional Application Expired
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2004-10-22 | TRNA |
Transmittal of New Application | 5 | View | |
| 2004-10-22 | SPEC |
Specification | 5 | View | |
| 2004-10-22 | CLM |
Claims | 1 | View | |
| 2004-10-22 | ABST |
Abstract | 1 | View | |
| 2004-10-22 | DRW |
Drawings-only black and white line drawings | 4 | View | |
| 2004-10-22 | WFEE |
Fee Worksheet (SB06) | 1 | View | |
| 2004-10-22 | ADS |
Application Data Sheet | 2 | View |
Inventors
Chun-Ying Chen
Irvine, CA
Attorneys & Agents of Record
Prosecution
- Customer No.
- 26111
- Docket No.
- 1875.7120000/RES/JT
- Confirmation No.
- 5406
Child
Claims priority from a provisional application
→
App. 11/473,043
· US 7,705,463
Filed 2006-06-23
· Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362
Child
Claims priority from a provisional application
→
App. 11/084,784
· US 7,091,617
Filed 2005-03-21
· Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362
No recorded assignments were found for this patent.
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Quick Facts
- App. No.
- 60/620,966
- Filed
- 2004-10-22
External Links