IP Library › Patent Application 60684431
Patent Application Provisional
App. No. 60/684,431 · Confirmation No. 6557

Method for optimizing direct wafer bond line width for reduction of parasitic capacitance in MEMS accelerometers

Provisional Application Expired
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 Code Description Pages PDF
2005-05-25 TRNA Transmittal of New Application 2 View
2005-05-25 SPEC Specification 3 View
2005-05-25 DRW Drawings-only black and white line drawings 1 View
2005-05-25 WFEE Fee Worksheet (SB06) 1 View
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Quick Facts
App. No.
60/684,431
Filed
2005-05-25