Forming transistor gate structures in a semiconductor using a mask layer over an insulating layer
A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.
1. A method comprising:
forming in a semiconductor body source and drain regions of a plurality of transistors constituting a select-line driving circuit that drives a select-line in response to selection information;
forming an insulating layer over the semiconductor body including the source and drain regions;
forming on the insulating layer a mask layer including a line-shaped opening such that the line-shaped opening is positioned over respective parts of the source and drain regions of the transistors with an intervention of the insulating layer; and
forming a plurality of contact plugs each electrically connected to an associated one of the source and drain regions by use of a line SAC (Self-Align Contact) technique in which of the insulation layer is selectively removed by using the mask layer.
2. The method as claimed in claim 1 , wherein the select-line is at least one of word and column lines.
3. The method as claimed in claim 1 , wherein the line-shaped opening is provided along a direction substantially orthogonal to the select-line.
4. A method comprising:
forming a plurality of gate structures on an active region in line, each of the gate structures comprising a gate electrode and an insulating film covering the gate electrode, the gate structures being respectively for a plurality of transistors each driving an associated one of word lines or column lines;
forming interlayer insulating layer over the active region on which the gate structures are formed;
forming a mask layer on the interlayer insulation layer, the mask layer having at least one opening, the opening being elongated to cross respective portions of the gate structures on the active region in which a plurality of contact holes for source and drain region of the transistors are to be formed;
selectively removing the interlayer insulation layer by using the mask layer and the insulating film as a mask to form the contact holes; and
forming contact plugs in the contact holes.
5. The method as claimed in claim 4 , wherein the opening is provided in a direction substantially orthogonal to the word of column lines.
6. The method as claimed in claim 4 , wherein the gate structures are provided in a direction substantially orthogonal to the word lines.
7. The method as claimed in claim 6 , wherein the gate structures are provided to form a plurality of rows.
8. The method as claimed in claim 4 , wherein each of the contact holes are formed between associated adjacent two of the gate structures.
9. A method comprising:
forming a plurality of gate structures on an active region in line, each of the gate structures comprising a gate electrode and an insulating film covering the gate electrode, the gate structures being respectively for a plurality of transistors, wherein the plurality of transistors are formed in a memory core region;
forming interlayer insulating layer over the active region on which the gate structures are formed;
forming a mask layer on the interlayer insulation layer, the mask layer having at least one opening, the opening being elongated to cross respective portions of the gate structures on the active region in which a plurality of contact holes for source and drain region of the transistors are to be formed;
selectively removing the interlayer insulation layer by using the mask layer and the insulating film as a mask to form the contact holes; and
forming contact plugs in the contact holes.
10. The method as claimed in claim 9, wherein the plurality of transistors are formed in a sense amplifier area.
11. The method as claimed in claim 9, wherein the memory core region includes at least word line driving circuitry, decoding circuitry, sense amplifier circuitry, and a memory cell area.
12. The method as claimed in claim 9, wherein each of the contact holes are formed between associated adjacent two of the gate structures.