Memory device and controlling method of the same
A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.
1. A memory device comprising:
a memory which includes memory areas; and
a controller configured to, upon receipt of write data, write data in the memory areas while managing correspondence between addresses of write data and memory areas which store corresponding write data, wherein
a plurality of the memory areas constitute a management unit,
the controller is configured:
to receive a start command and, after the start command, a first write command to a first management unit to perform sequential writes to the first management unit in a sequential mode; and
to receive a second write command to a second management unit, the second management unit having an address that is non-sequential with an address of the first management unit, to end the sequential mode to perform writes to the second management unit to invalidate data in the first management unit which has not been updated by writes to the first management unit and to maintain data in the second management unit which has not been updated by writes to the second management unit.
2. The device according to claim 1 , wherein
the controller comprises a register holding information on a speed of data writing to the memory areas.
3. The device according to claim 1 , wherein
upon receipt of a data writing instruction, the controller prepares a work area temporarily secured for an address group which will contain the address of the write data,
the write data is written in the work area, and
the work area consists of only unwritten memory areas which contain no effective data.
4. The device according to claim 1 , wherein the controller
writes in a first work area first pieces of data which have predetermined association with each other and have addresses which belong to a first address group, and
writes in a second work area second pieces of data which have a predetermined association with each other and have addresses which belong to a second address group.
5. The device according to claim 1 , wherein
the memory is able to have data written in units of one memory area, and is able to have data erased in units of one erase unit which consists of successive memory areas.
6. A method of controlling a memory device comprising a memory comprising memory areas and a controller, the method comprising:
upon receipt of write data, writing data in the memory areas while managing correspondence between addresses of the write data and memory areas which store corresponding write data, a plurality of the memory areas constituting a management unit;
receiving a start command and, after the start command, a first write command to a first management unit to perform sequential writes to the first management unit in a sequential mode; and
receiving a second write command to a second management unit, the second management unit having an address that is non-sequential with an address of the first management unit, to end the sequential mode to perform writes to the second management unit to invalidate data in the first management unit which has not been updated by writes to the first management unit and to maintain data in the second management unit which has not been updated by writes to the second management unit.
7. The method according to claim 6 , wherein
the controller comprises a register holding information on a speed of data writing to the memory areas.
8. The method according to claim 6 , wherein
upon receipt of a data writing instruction, the controller prepares a work area temporarily secured for an address group which will contain the address of the write data,
the write data is written in the work area, and
the work area consists of only unwritten memory areas which contain no effective data.
9. The method according to claim 6 , wherein the controller
writes in a first work area first pieces of data which have a predetermined association with each other and have addresses which belong to a first address group, and
writes in a second work area second pieces of data which have a predetermined association with each other and have addresses which belong to a second address group.
10. The method according to claim 6 , wherein the memory is able to have data written in units of one memory area, and is able to have data erased in units of one erase unit which consists of successive memory areas.
11. A memory system comprising a memory device and a host device connectable to the memory device, the memory device comprising:
a memory which includes memory areas; and
a controller configured to, upon receipt of write data, write data in the memory areas while managing correspondence between addresses of write data and memory areas which store corresponding write data, wherein
a plurality of the memory areas constitutes a management unit,
the controller is configured:
to perform, upon receipt of a write request including a sequential write start command, a first write command to a first management unit, and write data items having serial addresses in the first management unit, sequential writes of the write data items to the first management unit in a sequential mode, no data item that has been stored in the first management unit before receipt of the write request and has not been updated by the write request being stored in the first management unit, the first write command being received after the sequential write start command without any command therebetween, and the write data items being received after the first write command; and
to end, upon receipt of a second write command to a second management unit having an address that is non-sequential with an address of the first management unit in the sequential mode, the sequential mode to perform writes to the second management unit to invalidate data in the first management unit which has not been updated by writes to the first management unit and to maintain data in the second management unit which has not been updated by writes to the second management unit, and
the host device is configured:
to transmit to the memory device the sequential write start command and the first write command after the sequential write start command, and
to transmit to the memory device the second write command to the second management unit.
12. The memory system according to claim 11, wherein the controller comprises a register holding information on a speed of data writing to the memory areas.
13. The memory system according to claim 11, wherein upon receipt of a data writing instruction, the controller prepares a work area temporarily secured for an address group which will contain the address of the write data, the write data is written in the work area, and the work area consists of only unwritten memory areas which contain no effective data.
14. The memory system according to claim 11, wherein the controller writes in a first work area first pieces of data which have a predetermined association with each other and have addresses which belong to a first address group, and writes in a second work area second pieces of data which have a predetermined association with each other and have addresses which belong to a second address group.
15. The memory system according to claim 11, wherein the memory is able to have data written in units of one memory area, and is able to have data erased in units of one erase unit which consists of successive memory areas.