Gate driving circuit and display device using the same
A display device according to the present disclosure comprises a substrate including a display area and a non-display area, pixel circuits each including at least one n-type transistor and at least one p-type transistor and arranged in the display area, and a gate driving circuit included in the non-display area and outputting a first scan signal for applying a data voltage to driving transistors of the pixel circuits for an initialization time and a second scan signal that represents a same logic voltage as the first scan signal for the initialization time and represents a logic voltage reverse to the first scan signal for a sampling time. A first scan signal generator and a second scan signal generator are integrated using nodes Q/QB of a logic circuit to reduce a bezel size.
1 . A gate driving circuit comprising:
a logic signal generator including a first node and a second node outputting a logic signal reverse to a logic signal of the first node and outputting a carry signal; and
a scan signal generator including a first scan signal generator and a second scan signal generator, wherein the first scan signal generator generates a first scan signal and the second scan signal generator generates a second scan signal for applying a data voltage to one or more driving transistors of one or more pixel circuits for an initialization time by sharing the first node and the second node of the logic signal generator, and wherein the second scan signal generator generates a second scan signal that is a same logic voltage signal as the first scan signal for the initialization time and is a logic voltage signal reverse to the first scan signal for a sampling time by sharing the first node and the second node of the logic signal generator.
2 . The gate driving circuit of claim 1 , wherein an initialization time of 4 horizontal periods and a sampling time of 1 horizontal period are provided using 6-phase clock signals.
3 . The gate driving circuit of claim 1 , wherein an initialization time of 6 horizontal periods and a sampling time of 1 horizontal period are provided using 8-phase clock signals.
4 . The gate driving circuit of claim 1 , wherein the logic signal generator includes a first transistor having a gate electrode connected to the first node and a second transistor serially connected to the first transistor and having a gate electrode connected to the second node and outputs a carry pulse signal through a node shared by the first transistor and the second transistor;
wherein the first scan signal generator includes a third transistor having a gate electrode connected to the first node and a fourth transistor serially connected to the third transistor and having a gate electrode connected to the second node and outputs the first scan signal through a node shared by the third transistor and the fourth transistor; and
wherein the second scan signal generator includes a fifth transistor having a gate electrode connected to the first node and a sixth transistor serially connected to the fifth transistor and having a gate electrode connected to the second node and outputs the second scan signal through a node shared by the fifth transistor and the sixth transistor.
5 . The gate driving circuit of claim 4 , wherein the first to sixth transistors are p-type transistors.
6 . The gate driving circuit of claim 4 , wherein a first clock signal is supplied to one terminal of the first transistor, a second high-level voltage is supplied to one terminal of the second transistor, a first high-level voltage is supplied to one terminal of the third transistor, a first low-level voltage is supplied to one terminal of the fourth transistor, a fourth clock signal is supplied to one terminal of the fifth transistor, and the second high-level voltage is supplied to one terminal of the sixth transistor.
7 . The gate driving circuit of claim 6 , wherein a capacitor is disposed between a connecting point of the first node and the gate electrode of the fifth transistor and the node shared by the fifth transistor and the sixth transistor.
8 . The gate driving circuit of claim 7 , wherein the first scan signal generator includes a first signal transmission transistor having a source electrode connected to the first node and a drain electrode connected to the gate electrode of the third transistor and turned on all the time by receiving a second low-level voltage through a gate electrode, and
wherein the second scan signal generator includes a second signal transmission transistor having a source electrode connected to the first node and a drain electrode connected to the gate electrode of the fifth transistor and turned on all the time by receiving the second low-level voltage through a gate electrode.
9 . The gate driving circuit of claim 4 , wherein the logic signal generator, the first scan signal generator and the second scan signal generator output a high-level voltage when first to fifth clock signals are a low-level voltage and a start pulse signal and a sixth clock signal are the low-level voltage,
the logic signal generator outputs the low-level voltage and the first scan signal generator and the second scan signal generator output the high-level voltage when the first clock signal is the low-level voltage and the start pulse signal and the second to sixth clock signals are the high-level voltage,
the logic signal generator and the first scan signal generator output the high-level voltage and the second scan signal generator outputs the high-level voltage when the fourth clock signal is the low-level voltage and the start pulse signal, the first to third clock signals and the fifth and sixth clock signals are the high-level voltage, and
the logic signal generator and the second scan signal generator output the high-level voltage and the first scan signal generator outputs the low-level voltage when the fifth clock signal is the low-level voltage and the start pulse signal, the first to fourth clock signals and the sixth clock signal are the high-level voltage.
10 . A display device comprising:
a substrate including a display area and a non-display area;
pixel circuits each including a driving transistor for transferring current necessary to operate a light-emitting diode according to a switching operation and arranged in the display area; and
the gate driving circuit according to claim 1 included in the non-display area.
11 . The display device of claim 10 , wherein each pixel circuit includes at least one oxide semiconductor transistor and at least one polysilicon transistor.
12 . The display device of claim 10 , wherein each pixel circuit includes a first scan transistor configured to receive a first scan signal and apply the first scan signal to a gate electrode of the driving transistor, and a second scan transistor configured to receive a second scan signal and perform a switching operation for compensating for the driving transistor.
13 . The display device of claim 12 , wherein the first scan transistor is an oxide transistor and the second scan transistor is a silicon transistor.
14 . The display device of claim 12 , wherein the driving transistor is an oxide transistor.
15 . The display device of claim 12 , wherein the driving transistor is a silicon transistor.
16 . The display device of claim 12 , wherein the driving transistor has a channel formed of a semiconductor oxide.
17 . The display device of claim 12 , wherein the second scan transistor is a p-type metal-oxide-semiconductor silicon transistor.
18 . The display device of claim 12 , wherein the second scan transistor is an n-type metal-oxide-semiconductor silicon transistor.
19. The gate driving circuit of claim 1 , wherein the second scan signal is a logic voltage signal that is opposite to the first scan signal during a sampling time.
20. The gate driving circuit of claim 1 , wherein the gate driving circuit uses 6-phase clock signals.
21. The gate driving circuit of claim 20 , wherein an initialization time of 4 horizontal periods and a sampling time of 1 horizontal period are provided using the 6-phase clock signals.
22. The gate driving circuit of claim 20 , wherein the logic signal generator outputs the carry signal based on a start pulse signal having a voltage level that is a same as a voltage level of at least one of the 6-phase clock signals.
23. The gate driving circuit of claim 1 , wherein the logic signal generator includes a first transistor and a second transistor that is serially connected to the first transistor at a first output node, the first transistor having a gate electrode connected to the first node and the second transistor having a gate electrode that is connected to the second node, the logic signal generator configured to output a carry signal at the first output node.
24. The gate driving circuit of claim 1 , wherein the first scan signal generator includes a third transistor and a fourth transistor that is serially connected to the third transistor at a second output node, the third transistor having a gate electrode connected to the first node and the fourth transistor having a gate electrode connected to the second node, the first scan signal generator configured to output the first scan signal at the second output node.
25. The gate driving circuit of claim 1 , wherein the second scan signal generator includes a fifth transistor and a sixth transistor that is serially connected to the fifth transistor at a third output node, the fifth transistor having a gate electrode connected to the first node and the sixth transistor having a gate electrode connected to the second node, the second scan signal generator configured to output the second scan signal at the third output node.
26. The gate driving circuit of claim 23 , wherein the logic signal generator further comprises a first capacitor having a first electrode and a second electrode, the first electrode of the first capacitor connected to the first node and the second electrode of the first capacitor connected to the first output node of the logic signal generator.
27. The gate driving circuit if claim 25 , wherein the second scan signal generator further includes a second capacitor having a first electrode and a second electrode, the first electrode of the second capacitor connected to the gate electrode of the fifth transistor and the second electrode of the second capacitor connected to the third output node of the second scan signal generator.
28. The gate driving circuit of claim 1 , wherein the first scan signal generator is configured to generate the first scan signal based on a first high-level voltage, and the second scan signal generator is configured to generate the second scan signal based on a second high-level voltage that is different from the first high-level voltage.
29. The gate driving circuit of claim 28 , wherein the logic signal generator is configured to generate a carry signal based on the second high-level voltage.
30. The gate driving circuit of claim 1 , wherein the logic signal generator is configured to start an operation of generating the carry signal based on a start pulse signal.
31. A display device comprising:
a substrate including a display area and a non-display area;
a plurality of pixel circuits in the display area, each pixel circuit of the plurality of pixel circuits including a driving transistor configured to transfer current to operate a light-emitting diode according to a switching operation; and
a gate driving circuit in the non-display area, the gate driving circuit including:
a logic signal generator including a first node and a second node outputting a logic signal reverse to a logic signal of the first node and outputting a carry signal; and
a scan signal generator including a first scan signal generator configured to generate a first scan signal and a second scan signal generator configured to generate a second scan signal for applying a data voltage to one or more driving transistors of one or more pixel circuits of the plurality of pixel circuits for an initialization time,
wherein the first scan signal generator and the second scan signal generator respectively generate the first scan signal and the second scan signal by sharing the first node and the second node of the logical signal generator, and
wherein the second scan signal is a same logic voltage signal as the first scan signal for the initialization time.
32. A display device comprising:
a display panel including a plurality of pixel circuits; and
a data driving circuit and a scan driving circuit configured to drive the plurality of pixel circuits,
wherein each of the plurality of pixel circuits includes an oxide transistor,
wherein the scan driving circuit includes a logical signal generator and a scan signal generator, the logic signal generator having a first node and a second node, and
wherein the scan signal generator includes a first scan signal generator and a second scan signal generator that are connected to the first node and the second node of the logic signal generator, the first scan signal generator configured to generate a first scan signal and the second scan signal generator configured to generate a second scan signal for applying a data voltage to one or more driving transistors of one or more pixel circuits of the plurality of pixel circuits for an initialization time, and
wherein the second scan signal is a same logic voltage signal as the first scan signal for the initialization time.
33. The display device of claim 32 , wherein each of the plurality of pixel circuits further includes a driving transistor, a first scan transistor configured to receive the first scan signal and apply a data voltage to a gate electrode of the driving transistor, a capacitor configured to store the data voltage, and a second transistor configured to receive the second scan signal and perform a switching operation for compensating for the driving transistor.
34. The display device of claim 33 , wherein the driving transistor is the oxide transistor.
35. The display device of claim 33 , wherein one of the first scan transistor and the second scan transistor is an oxide transistor and another one of the first scan transistor and the second scan transistor is a polysilicon transistor.
36. The display device of claim 33 , wherein the first scan transistor receives the first scan signal during an initialization time, and the second scan transistor receives the second scan signal during a sampling time.
37. The display device of claim 36 , wherein the initialization time having 4 horizontal periods and the sampling time having 1 horizontal period are provided using 6-phase clock signals.
38. The display device of claim 32 , wherein the logic signal generator includes a first transistor and a second transistor that is serially connected to the first transistor at a first output node, the first transistor having a gate electrode connected to the first node and the second transistor having a gate electrode that is connected to the second node, the logic signal generator configured to output a carry pulse signal at the first output node.
39. The display device of claim 32 , wherein the first scan signal generator includes a third transistor and a fourth transistor that is serially connected to the third transistor at a second output node, the third transistor having a gate electrode connected to the first node and the fourth transistor having a gate electrode connected to the second node, the first scan signal generator configured to output the first scan signal at the second output node.
40. The display device of claim 32 , wherein the second scan signal generator includes a fifth transistor and a sixth transistor that is serially connected to the fifth transistor at a third output node, the fifth transistor having a gate electrode connected to the first node and the sixth transistor having a gate electrode connected to the second node, the second scan signal generator configured to output the second scan signal at the third output node.